sdram
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：506KB
下载次数：9
上传日期：2015-08-11 11:01:55
上 传 者：
mingmingjiang
说明： ISE14.4环境编程，XILINX spartan3E,SDRAM完整编程
(xilinx sdram)
文件列表:
sdram\CLK_GEN.cmd_log (366, 2011-09-25)
sdram\CLK_GEN.spl (97, 2011-09-25)
sdram\CLK_GEN.sym (1360, 2011-09-25)
sdram\CLK_GEN.v (2919, 2011-09-25)
sdram\CLK_GEN_arwz.ucf (731, 2011-09-25)
sdram\coregen.cgc (2049, 2011-09-25)
sdram\coregen.cgp (518, 2011-09-25)
sdram\data_ctl.cmd_log (298, 2011-09-25)
sdram\data_ctl.spl (143, 2011-09-25)
sdram\data_ctl.sym (2496, 2011-09-25)
sdram\data_ctl.v (1338, 2012-11-21)
sdram\ipcore_dir\CLK_GEN.cgc (6798, 2011-09-25)
sdram\ipcore_dir\CLK_GEN.cgp (522, 2011-09-25)
sdram\ipcore_dir\CLK_GEN_flist.txt (95, 2011-09-25)
sdram\ipcore_dir\CLK_GEN_xmdf.tcl (1684, 2011-09-25)
sdram\ipcore_dir\xaw2verilog.log (37, 2011-09-25)
sdram\ipcore_dir\CLK_GEN_arwz.ucf (731, 2015-08-04)
sdram\ipcore_dir\CLK_GEN.v (2657, 2015-08-04)
sdram\ipcore_dir\CLK_GEN.xaw (3252, 2015-08-04)
sdram\iseconfig\testsdram.projectmgr (7382, 2015-08-10)
sdram\iseconfig\top.xreport (19471, 2015-08-10)
sdram\pa.fromHdl.tcl (959, 2011-09-25)
sdram\pa.fromNetlist.tcl (585, 2011-09-25)
sdram\planAhead.ngc2edif.log (1033, 2011-09-25)
sdram\planAhead_run_1\planAhead.jou (1019, 2011-09-25)
sdram\planAhead_run_1\planAhead.log (3968, 2011-09-25)
sdram\planAhead_run_1\planAhead_run.log (2169, 2011-09-25)
sdram\planAhead_run_1\testsdram.data\constrs_1\fileset.xml (335, 2011-09-25)
sdram\planAhead_run_1\testsdram.data\runs\impl_1.psg (391, 2011-09-25)
sdram\planAhead_run_1\testsdram.data\runs\runs.xml (190, 2011-09-25)
sdram\planAhead_run_1\testsdram.data\sources_1\fileset.xml (542, 2011-09-25)
sdram\planAhead_run_1\testsdram.data\wt\webtalk_pa.xml (1249, 2011-09-25)
sdram\planAhead_run_1\testsdram.ppr (277, 2011-09-25)
sdram\planAhead_run_2\planAhead.jou (1412, 2011-09-25)
sdram\planAhead_run_2\planAhead.log (12232, 2011-09-25)
sdram\planAhead_run_2\planAhead_run.log (1023, 2011-09-25)
sdram\planAhead_run_2\testsdram.data\constrs_1\fileset.xml (335, 2011-09-25)
sdram\planAhead_run_2\testsdram.data\sources_1\fileset.xml (583, 2011-09-25)
sdram\planAhead_run_2\testsdram.data\wt\webtalk_pa.xml (1335, 2011-09-25)
... ...
The following files were generated for 'CLK_GEN' in directory
C:\xilinxtest\testsdram\testsdram\ipcore_dir\
CLK_GEN_readme.txt:
Text file indicating the files generated and how they are used.
CLK_GEN_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
CLK_GEN_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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