project_10_first_d1_VGA
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：791KB
下载次数：12
上传日期：2015-08-14 10:26:46
上 传 者：
lrihuan
说明： FPGA EP4CE40F23C6 ADV7123 彩条输出源程序，验证可用
(FPGA EP4CE40F23C6 ADV7123 color bar output source, verify Available)
文件列表:
project_10_first_d1_VGA\ALINX3402_EP4CE15F23C8 .tcl (21159, 2013-05-27)
project_10_first_d1_VGA\ALINX3402_EP4CE30F23C6.tcl (21159, 2013-05-27)
project_10_first_d1_VGA\ddr2_phy_autodetectedpins.tcl (1474, 2014-04-15)
project_10_first_d1_VGA\ip_core\ddr\altmemphy-library\auk_ddr_hp_controller.ocp (488, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_addr_cmd.v (24623, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_addr_cmd_wrap.v (55196, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_arbiter.v (52523, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_buffer.v (4029, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_buffer_manager.v (7962, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_burst_gen.v (68287, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_burst_tracking.v (3799, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_cmd_gen.v (120674, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_controller.v (174874, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_controller_st_top.v (94389, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_csr.v (51657, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_dataid_manager.v (37178, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ddr2_odt_gen.v (18004, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ddr3_odt_gen.v (17824, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_define.iv (1402, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_decoder.v (14559, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_decoder_32_syn.v (32582, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_decoder_64_syn.v (58573, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_encoder.v (9895, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_encoder_32_syn.v (12982, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_encoder_64_syn.v (21043, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_ecc_encoder_decoder_wrapper.v (48802, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_fifo.v (7367, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_input_if.v (9812, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_list.v (7603, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_lpddr2_addr_cmd.v (16892, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_mm_st_converter.v (10940, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_odt_gen.v (14233, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_rank_timer.v (119561, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_rdata_path.v (51123, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_rdwr_data_tmg.v (201262, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_sideband.v (72900, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_tbp.v (170772, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_timing_param.v (67710, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_ddrx_wdata_path.v (50682, 2013-03-21)
project_10_first_d1_VGA\ip_core\ddr\alt_mem_phy_defines.v (5281, 2013-03-21)
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