文件列表:

wave_all_csc_top_tb.do (2736, 2002-09-05)
CSC\CSC.bld (1908, 2005-10-25)
CSC\CSC.dsk (906, 2005-10-25)
CSC\CSC.hpj (10934, 2005-10-25)
CSC\CSC.v (3583, 2004-03-15)
CSC\CSC_templateDiagram.btim (2562, 2005-10-25)
CSC\StimulusAndResults.bk (2562, 2005-10-25)
CSC\StimulusAndResults.btim (2562, 2005-10-25)
CSC\syncad.v (379, 2004-03-15)
CSC\wavelib.v (39793, 2004-03-15)
CSC\wavelib_exact.v (95228, 2004-03-15)
CSC\wavelib_inertial.v (68513, 2004-03-15)
CSC\wavelib_standard.v (37688, 2004-03-15)
CSC\wavelib_transport.v (71682, 2004-03-15)
CSC\lib\verilog\cds.lib (45, 2004-05-25)
CSC\lib\verilog\hdl.var (204, 2004-05-04)
CSC\lib\verilog\inputfiles.txt (246, 2004-06-15)
CSC\lib\verilog\sram.v (1482, 2004-03-15)
CSC\lib\verilog\tbfifosemaphore.v (2575, 2004-03-15)
CSC\lib\verilog\tbsyslog.v (852, 2005-01-12)
CSC\lib\verilog\tb_clock_max.v (2246, 2004-03-15)
CSC\lib\verilog\tb_clock_max_inverted.v (2250, 2004-03-15)
CSC\lib\verilog\tb_clock_min.v (2242, 2004-03-15)
CSC\lib\verilog\tb_clock_minmax.v (2757, 2004-03-15)
CSC\lib\verilog\tb_clock_minmax_inverted.v (2763, 2004-03-15)
CSC\lib\verilog\tb_clock_min_inverted.v (2248, 2004-03-15)
CSC\lib\verilog\tb_clock_typ.v (2258, 2004-03-15)
CSC\lib\verilog\tb_clock_typ_inverted.v (2266, 2004-03-15)
CSC\lib\verilog\tb_divider_clock.v (2342, 2004-06-15)
CSC\lib\verilog\tb_divider_clock_minmax.v (4704, 2004-06-15)
CSC_1\.untf (0, 2007-07-27)
CSC_1\automake.log (0, 2007-07-27)
CSC_1\const_mult.v (2423, 2007-07-27)
CSC_1\csc.v (16030, 2007-07-27)
CSC_1\CSC_1.dhp (2849, 2007-07-27)
CSC_1\CSC_1.ise (4514, 2007-07-27)
CSC_1\CSC_1.ise_ISE_Backup (4514, 2007-07-27)
CSC_1\csc_summary.html (2426, 2007-07-27)
CSC_1\csc_top.bld (701, 2007-07-27)
CSC_1\csc_top.cel (0, 2007-07-27)
... ...

**************************************************************************** ************************* XAPP637 Reference design ************************* **************************************************************************** Here's some specifics to be known when using this reference design (csc_top). This reference dsign has been tested against ISE 4.2.03i, running entirely with the GUI. * This reference design supports 8-bit and 10-bit input/output through generics (VHDL) or parameters (Verilog). * The internal coefficients are coded through constants (VHDL) or parameters (Verilog), from 8- to 13-bit coefficients. Those coefficients can be changed in csc.vhd or csc.v * An Excel sheet (named "RGBColorBars_testvectors.xls") has been provided to detail the coefficient quantization. It gives a good start to understand the trade-offs in choosing the number of bits per coefficient affecting the output result. *** VHDL ref design: ------------------- Hdl sources are located in Hdl/ - csc_top.vhd : top-level file wrapper including register for input/output - csc.vhd : csc computation, calling the constant multipliers - const_mult.vhd : constant multiplier code - csc_top_tb.vhd : testbench (change generic TESTBENCH_OUT_SIZE to switch from 8- to 10-bit) Simulation ouputs can be observed in file "trace_csc.txt"... ISE project is located in CSC/ - CSC.npl : ISE project file - csc_top.ucf : user constraints file for timings - csc_top_tb.udo : user DO file calling the wave_all_csc_top_tb.do file - wave_all_csc_top_tb.do : interesting signals to see in MTI's wave window Individual implementation compilations for each devices reported in xapp637 are located in Top/ Each combination of input/output vs coefficient quantization (netlist_10bit_13-11-10bit, etc.) are provided as is for each device family (Virtex to Virtex2Pro). *** Workaround for VHDL gate-level simulation with timing: --------------------------------------------------------- It's required to add the generic declaration for the "csc_top" entity by hand in the "csc_top_timesim.vhd" file when doing the gate-level simulation. This is required to get the testbench to match the gate-level simualtion model of the FPGA (back-annotated model). The simualtion model doesn't get the generic declararion written, so it differs from behavioral model. If the generic declaration is not added, here is the MTI messages you'll get: ... # -- Loading entity csc_top # WARNING[1]: c:/designs/designs_projects_cores_tests/colorspaceconverter_xapp/vhdl/Hdl/csc_top_tb.vhd(193): No default binding for component: "csc_top". (Generic "top_out_size" is not on the entity) # vsim -lib work -***max /UUT=csc_top_timesim.*** -t 1ps testbench # Loading C:/Mentor/Modeltech_5.6/win32/../std.standard # Loading C:/Mentor/Modeltech_5.6/win32/../ieee.std_logic_11***(body) # Loading C:/Mentor/Modeltech_5.6/win32/../ieee.numeric_std(body) # Loading C:/Mentor/Modeltech_5.6/win32/../std.textio(body) # Loading work.testbench(behavior) # ** Warning: (vsim-3473) Component 'uut' is not bound. # Time: 0 ps Iteration: 0 Region: /testbench # ** Error: (vsim-SDF-3250) csc_top_timesim.***(0): Failed to find INSTANCE '/UUT'. # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./csc_top_tb.tdo PAUSED at line 10 ... See below for an extract of the "csc_top_timesim.vhd" file, see the two generic lines (one of those lines is commented out). Comment/uncomment the correct one. To locate the right entity, look for "entity csc_top" keyword. ... library IEEE; use IEEE.STD_LOGIC_11***.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity csc_top is generic ( TOP_OUT_SIZE : INTEGER := 8 ); -- uncomment to get 8-bit input & output... -- generic ( TOP_OUT_SIZE : INTEGER := 10 ); -- uncomment to get 10-bit input & output... port ( Reset : in STD_LOGIC := 'X'; ClockEnable : in STD_LOGIC := 'X'; Clock : in STD_LOGIC := 'X'; Cb : out STD_LOGIC_VECTOR ( 7 downto 0 ); Red : in STD_LOGIC_VECTOR ( 7 downto 0 ); Cr : out STD_LOGIC_VECTOR ( 7 downto 0 ); Blue : in STD_LOGIC_VECTOR ( 7 downto 0 ); Y : out STD_LOGIC_VECTOR ( 7 downto 0 ); Green : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end csc_top; ... *** Verilog ref design: ---------------------- Hdl sources are located in Hdl/ - csc_top.v : top-level file wrapper including register for input/output - csc.v : csc computation, calling the constant multipliers - const_mult.v : constant multiplier code - csc_top_tb.tf : testbench (change parameter TESTBENCH_OUT_SIZE to switch from 8- to 10-bit) Simulation ouputs can be observed in file "trace_csc.txt"... ISE project is located in CSC/ - CSC.npl : ISE project file - csc_top.ucf : user constraints file for timings - csc_top_tb.udo : user DO file calling the wave_all_csc_top_tb.do file - wave_all_csc_top_tb.do : interesting signals to see in MTI's wave window

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：