hydra
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：61319KB
下载次数：0
上传日期：2015-09-14 23:49:43
上 传 者：
sh-1993
说明： verilog中的可编程密码协处理器
(a programmable cryptographic coprocessor in verilog)
文件列表:
LICENSE (35121, 2015-09-15)
bluespec prototype (0, 2015-09-15)
bluespec prototype\hydra_ntru_tts (0, 2015-09-15)
bluespec prototype\hydra_ntru_tts\Hybrid.bsv (4303, 2015-09-15)
bluespec prototype\hydra_ntru_tts\Makefile (834, 2015-09-15)
bluespec prototype\hydra_ntru_tts\Tb.bsv (2082, 2015-09-15)
bluespec prototype\hydra_ntru_tts\Type.bsv (46, 2015-09-15)
bluespec prototype\hydra_ntru_tts\Unit.bsv (790, 2015-09-15)
bluespec prototype\hydra_ntru_tts\ntru_tb.h (39285, 2015-09-15)
bluespec prototype\hydra_ntru_tts\wiedemann_tb.h (11226, 2015-09-15)
documentation (0, 2015-09-15)
documentation\hydra.pdf (662380, 2015-09-15)
documentation\prototype.pdf (2877457, 2015-09-15)
implementation (0, 2015-09-15)
implementation\.compxlib.cfg (2916, 2015-09-15)
implementation\.recordref_modgen (0, 2015-09-15)
implementation\D_Cache.v (174259, 2015-09-15)
implementation\HYDRA.mcs (5767693, 2015-09-15)
implementation\HYDRA_NO_INST.mcs (5767693, 2015-09-15)
implementation\HYDRA_NO_INST_V2.mcs (5767693, 2015-09-15)
implementation\Hydra.gise (1398, 2015-09-15)
implementation\Hydra.xise (43645, 2015-09-15)
implementation\Hydra_controller_summary.html (3726, 2015-09-15)
implementation\Hydra_inst_wo_load.v (25383, 2015-09-15)
implementation\Hydra_inst_wo_load_new.v (18558, 2015-09-15)
implementation\Hydra_summary.html (3715, 2015-09-15)
implementation\I_Cache.v (70062, 2015-09-15)
implementation\I_cache_summary.html (3717, 2015-09-15)
implementation\I_cache_syn.edn (4872, 2015-09-15)
implementation\I_cache_syn.ncf (0, 2015-09-15)
implementation\MYIP_WRAPPER_summary.html (3722, 2015-09-15)
implementation\MasterSlave_TRI.gise (1301, 2015-09-15)
implementation\MasterSlave_TRI.htm (385, 2015-09-15)
implementation\MasterSlave_TRI.ise_mark (29, 2015-09-15)
implementation\MasterSlave_TRI.log (408, 2015-09-15)
implementation\MasterSlave_TRI.sdc (416, 2015-09-15)
implementation\MasterSlave_TRI.srl (1131626, 2015-09-15)
implementation\MasterSlave_TRI.sym (5116, 2015-09-15)
... ...
Hydra
=====
Hydra is [an energy efficient programmable cryptographic coprocessor supporting elliptic curve pairings over fields of large characteristics](https://github.com/polysome/hydra/blob/master/documentation/hydra.pdf).
This verilog implementation was developed at National Taiwan University.
Released as GPLv3 with permission of Chen-Mou Cheng.
近期下载者：
相关文件：
收藏者：