CoreUartTest
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：817KB
下载次数：24
上传日期：2015-09-21 12:12:07
上 传 者：
Ke$ha
说明： Actel FPGA UART 串口通信模块，调用Actel CoreUART IP核实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。
(Actel FPGA UART serial communication module, call Actel CoreUART IP core implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.)
文件列表:
CoreUartTest\component\Actel\DirectCore\COREUART\5.5.101\COREUART.cxf (573, 2015-09-14)
CoreUartTest\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf (437, 2015-09-10)
CoreUartTest\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.sdb (896, 2015-09-14)
CoreUartTest\component\work\DESIGN_IO\DESIGN_IO.cxf (413, 2015-09-10)
CoreUartTest\component\work\DESIGN_IO\DESIGN_IO.sdb (1357, 2015-09-14)
CoreUartTest\component\work\uart1\uart1.cxf (4754, 2015-09-10)
CoreUartTest\component\work\uart1\uart1.sdb (2425, 2015-09-10)
CoreUartTest\component\work\uart1\uart1.v (4680, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\coreparameters.v (466, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\mti\scripts\wave_vlog.do (1458, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\rtl\vlog\core\Clock_gen.v (13230, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\rtl\vlog\core\CoreUART.v (14210, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\rtl\vlog\core\fifo_256x8_pa3e.v (3329, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\rtl\vlog\core\Rx_async.v (21139, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\rtl\vlog\core\Tx_async.v (8852, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\rtl\vlog\test\user\testbnch.v (39102, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_0\uart1_uart1_0_COREUART.cxf (1883, 2015-09-10)
CoreUartTest\component\work\uart1\uart1_manifest.txt (1069, 2015-09-10)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\coreparameters.v (466, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\mti\scripts\wave_vlog.do (1458, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\rtl\vlog\core\Clock_gen.v (13258, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\rtl\vlog\core\CoreUART.v (14294, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\rtl\vlog\core\fifo_256x8_pa3e.v (3385, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\rtl\vlog\core\Rx_async.v (21167, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\rtl\vlog\core\Tx_async.v (8866, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\rtl\vlog\test\user\testbnch.v (39130, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\COREUART_0\uart_SmartDesign_COREUART_0_COREUART.cxf (1897, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\datasheet.xsl (34989, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\drcss.xsl (2676, 2015-09-10)
CoreUartTest\component\work\uart_SmartDesign\uart_SmartDesign.cxf (2535, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\uart_SmartDesign.sdb (3987, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\uart_SmartDesign.v (4261, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\uart_SmartDesign_DataSheet.xml (5590, 2015-09-14)
CoreUartTest\component\work\uart_SmartDesign\uart_SmartDesign_DRC.xml (1244, 2015-09-10)
CoreUartTest\component\work\uart_SmartDesign\uart_SmartDesign_manifest.txt (1244, 2015-09-14)
CoreUartTest\CoreUartTest.prjx (14880, 2015-09-14)
CoreUartTest\designer\impl1\run_designer_tool.log (814, 2015-09-14)
CoreUartTest\designer\impl1\run_designer_tool.tcl (306, 2015-09-14)
CoreUartTest\designer\impl1\run_pinrpt.tcl (246, 2015-09-14)
CoreUartTest\designer\impl1\uart_SmartDesign.adb (230912, 2015-09-14)
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