Proj_AND_V1
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：204KB
下载次数：1
上传日期：2015-09-24 02:33:35
上 传 者：
ecb_vhdl
说明： Basic vhdl code for and gate logic.
文件列表:
Proj_AND_V1\AND2.bld (938, 2013-10-30)
Proj_AND_V1\AND2.cmd_log (1028, 2013-10-30)
Proj_AND_V1\AND2.lso (6, 2013-10-30)
Proj_AND_V1\AND2.ncd (3166, 2013-10-30)
Proj_AND_V1\AND2.ngc (1201, 2013-10-30)
Proj_AND_V1\AND2.ngd (1985, 2013-10-30)
Proj_AND_V1\AND2.ngr (786, 2013-10-30)
Proj_AND_V1\AND2.par (6094, 2013-10-30)
Proj_AND_V1\AND2.pcf (217, 2013-10-30)
Proj_AND_V1\AND2.prj (22, 2013-10-30)
Proj_AND_V1\AND2.stx (0, 2013-10-30)
Proj_AND_V1\AND2.syr (9759, 2013-10-30)
Proj_AND_V1\AND2.tfi (108, 2013-10-30)
Proj_AND_V1\AND2.twr (1948, 2013-10-30)
Proj_AND_V1\AND2.twx (18639, 2013-10-30)
Proj_AND_V1\AND2.unroutes (155, 2013-10-30)
Proj_AND_V1\AND2.vhd (355, 2013-08-21)
Proj_AND_V1\AND2.xst (1062, 2013-10-30)
Proj_AND_V1\AND2_envsettings.html (9555, 2013-10-30)
Proj_AND_V1\AND2_fpga_editor.log (608, 2013-10-30)
Proj_AND_V1\AND2_guide.ncd (3166, 2013-10-30)
Proj_AND_V1\AND2_map.map (5923, 2013-10-30)
Proj_AND_V1\AND2_map.mrp (7958, 2013-10-30)
Proj_AND_V1\AND2_map.ncd (2522, 2013-10-30)
Proj_AND_V1\AND2_map.ngm (3380, 2013-10-30)
Proj_AND_V1\AND2_pad.csv (13763, 2013-10-30)
Proj_AND_V1\AND2_pad.txt (65028, 2013-10-30)
Proj_AND_V1\AND2_summary.html (13310, 2013-10-30)
Proj_AND_V1\AND2_xst.xrpt (10800, 2013-10-30)
Proj_AND_V1\deco_7seg.vhd (1127, 2013-11-06)
Proj_AND_V1\Div_Clk_26.vhd (1328, 2013-11-06)
Proj_AND_V1\Nexys3_Master.ucf (24319, 2011-06-06)
Proj_AND_V1\pa.fromNetlist.tcl (704, 2013-10-30)
Proj_AND_V1\par_usage_statistics.html (4134, 2013-11-06)
Proj_AND_V1\pepExtractor.prj (70, 2013-11-06)
Proj_AND_V1\planAhead.ngc2edif.log (431, 2013-10-30)
Proj_AND_V1\Proj_AND_V1.gise (17134, 2013-11-06)
Proj_AND_V1\Proj_AND_V1.xise (38148, 2013-11-06)
Proj_AND_V1\top_teste_and2_v1.bgn (6762, 2013-11-06)
Proj_AND_V1\top_teste_and2_v1.bit (464299, 2013-11-06)
... ...
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