USB3_a3p1000_9.1__
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9032KB
下载次数：18
上传日期：2015-09-26 15:26:40
上 传 者：
johu85
说明： 8bit10bit编解码、SPI解串、BAT656接受源码，并通过USB3.0 传送至PC机。经测试actel fpga 时钟频率100M可以满足320MB/s的传输速率
(8bit10bit encoding and decoding, SPI solution string, BAT656 accept the source code, and through USB3.0 to PC. After testing the FPGA Actel clock frequency 100M can meet the transmission rate of 320MB/s)
文件列表:
USB3_a3p1000_9.1\aaa.dpz (3915, 2014-06-09)
USB3_a3p1000_9.1\component\work\aaa\aaa.cxf (1150, 2014-06-09)
USB3_a3p1000_9.1\component\work\aaa\aaa.sdb (2914, 2014-06-12)
USB3_a3p1000_9.1\constraint\1.pdc (344, 2014-05-17)
USB3_a3p1000_9.1\constraint\data\1.pdc.ce (1408, 2014-05-17)
USB3_a3p1000_9.1\constraint\data\usb3_top_32bit_pin.pdc.ce (2357, 2014-11-21)
USB3_a3p1000_9.1\constraint\slaveFIFO2b_loopback_1_sdc.sdc (441, 2014-11-20)
USB3_a3p1000_9.1\constraint\usb3_top_32bit_pin.pdc (10021, 2014-06-15)
USB3_a3p1000_9.1\constraint\usb3_top_32bit_pin_20140517.rar (661, 2014-05-17)
USB3_a3p1000_9.1\designer\impl2\11111111\$$FlashPro_66705.L$$ (900, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\11111111\11111111.log (1235, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\11111111\11111111.pro (1986, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\11111111\projectData\slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb (151552, 2014-11-20)
USB3_a3p1000_9.1\designer\impl2\designer.log (20283, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\fifo_money.ide_des (199, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\pll_25_to_100.ide_des (202, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_fpga_top.ide_des (196, 2014-11-20)
USB3_a3p1000_9.1\designer\impl2\slavefifo2b_fpga_top_tb.ide_des (212, 2014-06-14)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback.tcl (1871, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1.adb (556032, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1.dtf\verify.log (233, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1.ide_des (883, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1.pdb (113664, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1.pdb.depends (0, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_fp\$$FlashPro_66705.L$$ (173, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_fp\projectData\slaveFIFO2b_loopback_1.pdb (113664, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_fp\slaveFIFO2b_loopback_1.log (1129, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_fp\slaveFIFO2b_loopback_1.pro (0, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1.adb (1168896, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1.dtf\verify.log (233, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1.ide_des (931, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1.pdb (150528, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1.pdb.depends (0, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1_fp\$$FlashPro_66705.L$$ (185, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1_fp\projectData\slaveFIFO2b_loopback_1_synthesis_1.pdb (150528, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1_fp\slaveFIFO2b_loopback_1_synthesis_1.log (1253, 2014-06-13)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback_1_synthesis_1_fp\slaveFIFO2b_loopback_1_synthesis_1.pro (0, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback__all_in_1_synthesis.adb (397312, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback__all_in_1_synthesis.dtf\verify.log (233, 2014-11-21)
USB3_a3p1000_9.1\designer\impl2\slaveFIFO2b_loopback__all_in_1_synthesis.ide_des (890, 2014-11-21)
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