xilinx_ddr3
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5892KB
下载次数：43
上传日期：2015-10-19 21:42:04
上 传 者：
peisongwei
说明： xilinx ddr3 开发， 实测好用
(xilinx ddr3 development, found handy)
文件列表:
spartan_ddr3\coregen.cgc (69513, 2015-03-26)
spartan_ddr3\coregen.cgp (522, 2015-03-26)
spartan_ddr3\iseconfig\mig_39_2.projectmgr (4272, 2015-06-08)
spartan_ddr3\iseconfig\mig_39_2.xreport (20624, 2015-08-25)
spartan_ddr3\mig.prj (3128, 2015-03-26)
spartan_ddr3\mig_39_2\docs\ug388.pdf (2172724, 2013-10-14)
spartan_ddr3\mig_39_2\docs\ug416.pdf (80254, 2013-10-14)
spartan_ddr3\mig_39_2\example_design\chipscope\ax516.cpj (101184, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\datasheet.txt (2432, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\log.txt (2606, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\mig.prj (3128, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\coregen.cgc (64563, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\coregen.cgp (520, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\coregen.log (1746, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\create_ise.bat (3266, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\example_top.bgn (9210, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.bit (464590, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.bld (95480, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.cdc (13980, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\example_top.cmd_log (1670, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.drc (2382, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ncd (1066022, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ngc (1685951, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ngd (3064881, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ngr (2424627, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.pad (15876, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.par (21540, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.pcf (507683, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.prj (1260, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ptwx (23126, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.stx (0, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.syr (601897, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.twr (251790, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.twx (287667, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ucf (11287, 2015-03-26)
spartan_ddr3\mig_39_2\example_design\par\example_top.unroutes (1032, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.ut (553, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.xpi (46, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top.xst (1175, 2015-06-08)
spartan_ddr3\mig_39_2\example_design\par\example_top_bitgen.xwbt (364, 2015-06-08)
... ...
The design files are located at
E:/Project/AX516/verilog/ddr3_test:
- mig_39_2.veo:
veo template file containing code that can be used as a model
for instantiating a CORE Generator module in a HDL design.
- mig_39_2.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
- mig_39_2_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
- mig_39_2_readme.txt:
Text file indicating the files generated and how they are used.
- mig_39_2_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
- mig_39_2.gise and mig_39_2.xise:
ISE Project Navigator support files. These are generated files and
should not be edited directly.
- mig_39_2 directory.
In the mig_39_2 directory, three folders are created:
- docs:
This folder contains Virtex-6 FPGA Memory Interface Solutions user guide
and data sheet.
- example_design:
This folder includes the design with synthesizable test bench.
- user_design:
This folder includes the design without test bench modules.
The example_design and user_design folders contain several other folders
and files. All these output folders are discussed in more detail in
Spartan-6 FPGA Memory Controller user guide (ug388.pdf) located in docs folder.
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