Camera_Interface_Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：340KB
下载次数：97
上传日期：2011-03-06 13:33:15
上 传 者：
jinjinxinyi
说明： 该源代码包是基于片上系统的摄像头接口的Verilog语言程序，它包括以下5部分：RTL源代码，测试平台，软件仿真C代码，FPGA综合时的sdc和ucf文件，说明文档。
(This source code package is the camera interface module based on the SoC use Verilog language. It has the following 5 parts: RTL code, testbench, software simulating C code, the sdc and ucf files for the FPGA synthiese, help document.)
文件列表:
Camera_Interface_Verilog\bench\verilog\camera_bench_defines.v (3563, 2003-10-17)
Camera_Interface_Verilog\bench\verilog\camera_bench_top.v (44688, 2010-07-16)
Camera_Interface_Verilog\bench\verilog\wb_master32.v (13437, 2003-05-12)
Camera_Interface_Verilog\bench\verilog\wb_master_behavioral.v (22990, 2003-05-12)
Camera_Interface_Verilog\bench\verilog\wb_master_defines.v (6766, 2010-06-01)
Camera_Interface_Verilog\bench\verilog\wb_slave_behavioral.v (10109, 2003-12-04)
Camera_Interface_Verilog\doc\camera_specification.pdf (467945, 2003-12-01)
Camera_Interface_Verilog\rtl\verilog\camera_async_reset_flop.v (4626, 2003-12-04)
Camera_Interface_Verilog\rtl\verilog\camera_cb_table.v (36470, 2003-11-25)
Camera_Interface_Verilog\rtl\verilog\camera_cr_table.v (36476, 2003-11-25)
Camera_Interface_Verilog\rtl\verilog\camera_defines.v (7462, 2003-12-04)
Camera_Interface_Verilog\rtl\verilog\camera_fifo.v (9871, 2003-10-17)
Camera_Interface_Verilog\rtl\verilog\camera_fifo_ctrl.v (13371, 2003-12-04)
Camera_Interface_Verilog\rtl\verilog\camera_io_calc.v (50386, 2003-11-18)
Camera_Interface_Verilog\rtl\verilog\camera_synchronizer_flop.v (5712, 2003-12-01)
Camera_Interface_Verilog\rtl\verilog\camera_sync_ctrl.v (11109, 2003-11-25)
Camera_Interface_Verilog\rtl\verilog\camera_top.v (13388, 2003-10-17)
Camera_Interface_Verilog\rtl\verilog\camera_tpram.v (20066, 2004-04-09)
Camera_Interface_Verilog\rtl\verilog\camera_wb_if.v (38800, 2003-11-25)
Camera_Interface_Verilog\rtl\verilog\camera_y_table.v (17807, 2003-11-25)
Camera_Interface_Verilog\rtl\verilog\timescale.v (22, 2003-05-12)
Camera_Interface_Verilog\sim\core_sw_simulator\b_cb.dat (1040, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\gen_yuv_rgb_files (17700, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\gen_yuv_rgb_files.c (10022, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\g_b_cb_case.dat (20328, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\g_cb.dat (1040, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\g_cr.dat (1040, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\rgb_out.dat (448, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\rgb_scale_out.dat (448, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\rgb_y.dat (1040, 2003-05-12)
Camera_Interface_Verilog\sim\core_sw_simulator\rgb_y_case.dat (7778, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\r_cr.dat (1040, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\r_g_cr_case.dat (20328, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\uyvy_in.dat (384, 2003-05-12)
Camera_Interface_Verilog\sim\core_sw_simulator\yuv422_to_rgb (19910, 2003-10-16)
Camera_Interface_Verilog\sim\core_sw_simulator\yuv422_to_rgb.c (14035, 2003-10-16)
Camera_Interface_Verilog\sim\rtl_sim\bin\artisan_file_list.lst (148, 2003-05-12)
Camera_Interface_Verilog\sim\rtl_sim\bin\cds.lib (87, 2003-05-12)
Camera_Interface_Verilog\sim\rtl_sim\bin\hdl.var (238, 2003-05-12)
Camera_Interface_Verilog\sim\rtl_sim\bin\ncelab.args (152, 2003-05-12)
... ...
How to run PCI Bridge simulation:
You have to have ncsim simulator available to run pci simulation.
Simulation is started by invoking the script run_pci_sim.scr in this directory.
It can take one argument as an option: xilinx or artisan.
If you want to run the simulation using xilinx RAM primitives, you have to provide glbl.v primitive with
path relative to this directory: ../../../../lib/xilinx/lib/glbl/glbl.v and
RAM primitives with following paths relative to this directory:
../../../../lib/xilinx/lib/unisims/RAMB4_S16_S16.v and
../../../../lib/xilinx/lib/unisims/RAM16X1D.v
Regression tests are still in preparation!
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