PC-CFR
所属分类:matlab编程
开发工具:matlab
文件大小:2545KB
下载次数:131
上传日期:2015-11-12 14:01:15
上 传 者:
aqu2008
说明: 采用matlab simulink编写的消峰参考设计,可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比,提高功放效率。
(Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier efficiency.)
文件列表:
pc_cfr_test_v3_1c.m (10178, 2007-11-28)
testcase1.mat (1993088, 2007-09-18)
pc_cfr_virtex4_v1_1_cw_bd.bmm (1098, 2007-10-17)
pc_cfr_virtex4_v1_1_cw.bit (1712616, 2007-10-17)
pc_cfr_virtex4_v1_1.mdl (1697702, 2007-10-17)
pc_cfr_virtex5_v1_1.mdl (1748754, 2007-10-17)
pc_cfr_virtex5_v1_1_cw_bd.bmm (1137, 2007-10-17)
pc_cfr_virtex5_v1_1_cw.bit (2502498, 2007-10-17)
pc_cfr_virtex5_v1_1_hwl.mdl (90401, 2007-10-19)
pc_cfr_virtex4_v1_1_hwl.mdl (90197, 2007-10-19)
ccdf.p (2603, 2007-10-19)
cfr_iteration_v42.p (7036, 2007-10-19)
cordic_abs_sin_cos.p (6061, 2007-10-19)
dec2tce.p (1098, 2007-10-19)
sigprops.p (4615, 2007-10-19)
simple_abs.p (385, 2007-10-19)
tc_round.p (1195, 2007-10-19)
tce2dec.p (1278, 2007-10-19)
check_pc_cfr_v1.m (3588, 2007-11-28)
*******************************************************************************
** 2007 Xilinx, Inc. All Rights Reserved.
** Confidential and proprietary information of Xilinx, Inc.
*******************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/ Version: 1.0
** \ \ Filename: readme_xapp1033.txt
** / / Date Last Modified: Wed Nov 28, 2007
** /___/ /\ Date Created: Wed Nov 28, 2007
** \ \ / \
** \___\/\___\
**
**Devices: Virtex-4, Virtex-5
**Purpose:
** Provide designers with a highly optimized solution for Crest Factor
** Reduction (CFR) that can be adapted to meet the needs of multiple
** air interfaces with minimum effort.
**Reference:
** XAPP1033: Peak Cancellation Crest Factor Reduction Reference Design
**Revision History:
** 1.0: Initial Xilinx release.
*******************************************************************************
**
** Disclaimer:
**
** Xilinx licenses this Design to you AS-IS with no warranty of any kind.
** Xilinx does not warrant that the functions contained in the Design will
** meet your requirements, that the Design will operate uninterrupted or be
** error-free, or that errors or bugs in the Design will be corrected.
** Xilinx makes no warranties or representations in regard to the results
** obtained from your use of the Design with respect to accuracy,
** reliability, or otherwise.
**
** XILINX MAKES NO REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS OR IMPLIED,
** STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES
** OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE.
** IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA, LOST PROFITS, OR
** FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, OR INDIRECT DAMAGES ARISING
** FROM YOUR USE OF THIS DESIGN.
*******************************************************************************
This readme file describes how to use the files that come with XAPP1033.
*******************************************************************************
Description of each file:
1. pc_cfr_virtex4_v1_1.mdl: System Generator design file for the Virtex-4
version of the PC-CFR reference design.
2. pc_cfr_virtex4_v1_1_hwl.mdl: Hardware in the loop version of
pc_cfr_virtex4_v1_1.
3. pc_cfr_virtex5_v1_1.mdl: System Generator design file for the Virtex-5
version of the PC-CFR reference design.
4. pc_cfr_virtex5_v1_1_hwl.mdl: Hardware in the loop version of
pc_cfr_virtex5_v1_1.
5. pc_cfr_virtex4_v1_1_cw.bit: Bit stream for hardware in the loop that targets
the ML402 board with Ethernet point-to-point cosimulation.
6. pc_cfr_virtex5_v1_1_cw.bit: Bit stream for hardware in the loop that targets
the ML506 board with Ethernet point-to-point cosimulation.
7. pc_cfr_virtex4_v1_1_cw_bd.bmm: Block memory map file needed for Ethernet
cosimulation.
8. pc_cfr_virtex5_v1_1_cw_bd.bmm: Block memory map file needed for Ethernet
cosimulation.
9. testcase1.mat: Test stimulus for CFR input data and cancellation pulse
coefficients corresponding to the six nonadjacent carriers case.
10. check_pc_cfr_v1.m: MATLAB script that compares the behavior of the System
Generator design to a bit-true model.
11. pc_cfr_test_v3_1c.m: MATLAB main program that is used to evaluate the
performance of the PC-CFR algorithm. Includes behavioral code for the
generation of baseband test data, pulse shaping and digital up conversion.
Generates dPAPR, EVM, and ACLR metrics. Generates CCDF and PSD plots of
CFR input and output.
12. ccdf.p: Function that generates CCDF plot and returns PAPR at 0.01%
probability of clip point.
13. cfr_iteration_v42.p: Function that models a single iteration of the PC-CFR
design.
14. cordic_abs_sin_cos.p: Function that moxdels the cordic_mag_sin_cos design
module.
15. dec2tce.p: Function that converts from two's-complement signed format to
unsigned format.
16. sigprops.p: Function that prints dBFS, PAPR, and max absolute value of real
and imaginary signal components.
17. simple_abs.p: Function that computes a hardware efficient approximation of
absolute value using a one's complement method.
18. tc_round.p: Function that performs a simple round.
19. tce2dec.p: Function that converts from unsigned format to two'scomplement
signed format.
*******************************************************************************
*******************************************************************************
The procedure for simulating the reference design is as follows:
1. Open the System Generator design file in Matlab.
a. pc_cfr_virtex4_v1_1.mdl for the Virtex-4 version
b. pc_cfr_virtex4_v1_1_hwl.mdl for the ML402 hardware co-sim version
c. pc_cfr_virtex5_v1_1.mdl for the Virtex-5 version
d. pc_cfr_virtex5_v1_1_hwl.mdl for the ML506 hardware co-sim version
2. Load the example stimulus file testcase1.mat into the Matlab workspace.
After loading the example stimulus file there will be two variables used by
the design: cfr_in and coefficients. The cfr_in variable is the CFR input
stimulus data and the coefficients variable contains the cancellation pulse
coefficients.
3. Hit the "Start Simulation" button located on the top of the Simulink window
containing the reference design.
4. After the simulation has completed, run the check_pc_cfr_v1 script from the
Matlab prompt. This script compares the output of the System Generator
design to a bit-true behavioral model. The result from running this script
should be a message indicating that the check passed along with some
statistics on the maximum peak delay found per iteration. For example, the
following results are obtained when using the above procedure and after
running for a simulation time of 2e5:
>> check_pc_cfr_v1
Maximum Peak Delay: 4 (i=10428)
Maximum Peak Delay: 4 (i=44382)
Check Passed!
>>
*******************************************************************************
*******************************************************************************
Additional Information:
Different stimulus and coefficient data can be generated using the Matlab
program pc_cfr_test_v3_1c.m. This program contains behavioral code that
generates the CFR input data based on a user specified carrier configuration.
It also generates the cancellation pulse coefficients for a user specified
number of taps. Furthermore, it provides a means to experiment with different
CFR model settings such as number of CPGs per iteration, number of iterations,
and PAPR targets. Finally, the program generates performance metrics such as
dPAPR, EVM, and ACLR along with plots of CCDF and PSD for the CFR input and
output. After running this program, the user may save the cfr_in and
coefficients variables into their own testcase.mat file to use as stimulus for
the System Generator design.
It is important to note that the reference design hardware contains four CPGs
per iteration and two iterations. Therefore, changing these parameters in the
Matlab program will result in behavior that is different than what is produced
by the System Generator design. Furthermore, the threshold value produced from
changing the PAPR_target parameter must be used to drive the threshold port of
the System Generator design. Finally, the filter_numtaps and filter_ram_we
ports must be driven by stimulus consistent with the cfr_ntaps variable in the
Matlab program.
The files with a ".p" extension are functions that are in the Matlab
pre-parsed, pseudo-code file format (P-file). They are provided solely as
support functions that are required by the pc_cfr_test_v3_1c.m and
check_pc_cfr_v1.m main programs.
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