xilinx_PCIeLogiCore
所属分类:VHDL/FPGA/Verilog
开发工具:Windows_Unix
文件大小:4409KB
下载次数:18
上传日期:2015-11-17 17:27:23
上 传 者:
laughing110
说明: 基于xilinx fpga的PCIE逻辑IP核
(thisis a xilinx_PCIeLogiCore)
文件列表:
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\components.vhd (28961, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\downstreamSim.gise (1064, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\downstreamSim.wcfg (33528, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\downstreamSim.xise (52445, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\mockApplication.vhd (18941, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\string_utilities_sim_pkg.vhd (15990, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\string_utilities_synth_pkg.vhd (47084, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\testbench_top.vhd (6469, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\time_utilities_pkg.vhd (8862, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\gtx_drp_chanalign_fix_3752_v6.vhd (9229, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\gtx_rx_valid_filter_v6.vhd (17824, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\gtx_tx_sync_rate_v6.vhd (18407, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\gtx_wrapper_v6.vhd (40743, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_2_0_rport_v6.vhd (107438, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_2_0_v6_rp.vhd (165948, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_brams_v6.vhd (12113, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_bram_top_v6.vhd (9563, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_bram_v6.vhd (16296, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_clocking_v6.vhd (16368, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_gtx_v6.vhd (33963, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_pipe_lane_v6.vhd (15451, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_pipe_misc_v6.vhd (8948, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_pipe_v6.vhd (62379, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_reset_delay_v6.vhd (5661, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pcie_upconfig_fix_3451_v6.vhd (6906, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pci_exp_usrapp_cfg.vhd (5831, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pci_exp_usrapp_pl.vhd (4756, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pci_exp_usrapp_rx.vhd (28104, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\pci_exp_usrapp_tx.vhd (5388, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\tests.vhd (10189, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\test_interface.vhd (99173, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\ipcore_dir\S6PCIeEP\simulation\dsport\xilinx_pcie_2_0_rport_v6.vhd (33644, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\doc\s6_pcie_ds718.pdf (184889, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\doc\s6_pcie_ug654.pdf (52979, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\example_design\pcie_app_s6.v (7674, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\example_design\pcie_app_s6.vhd (10009, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\example_design\PIO.v (5551, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\example_design\PIO.vhd (7327, 2010-05-26)
Designing a LogiCORE PCI Express System\labs\downstreamSim\SP605\VHDL\S6PCIeEP\example_design\PIO_32_RX_ENGINE.v (18903, 2010-05-26)
... ...
Core name: Xilinx Spartan-6 Integrated
Block for PCI Express
Version: 1.3
Release Date: April 19, 2010
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this
core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Spartan-6
Integrated Block for PCI Express(R) v1.3 solution. For the latest core
updates, see the product page at:
http://www.xilinx.com/products/ipcenter/S6_PCI_Express_Block.htm
2. NEW FEATURES
- ISE 12.1 software support
- VHDL source for testbench
- Support for ISIM
- Additional Part/Package support
3. SUPPORTED DEVICES
- Spartan-6 LXT / XA LXT / Q LXT
4. RESOLVED ISSUES
- V6 MMCM VCO changed from 500 MHz to 1000 MHz (in Root Port Model)
- Version fixed: 1.2 rev 1
- CR #543565
- AR #34341
- Timing error when implementing VHDL example design
- Version fixed: 1.2 rev 1
- CR #548007
- AR #34342
- Designs which use Multi-Vector MSI should check the number of allocated
vectors before generating an MSI interrupt
- Version fixed: N/A
- Previously mentioned as an issue in v1.1 but no longer an issue in v1.2
- CR #522729
- AR #32866
5. KNOWN ISSUES
The following are known issues for v1.3 of this core at time of release:
- N/A
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
04/19/2010 Xilinx, Inc. 1.3 ISE 12.1 support
03/09/2010 Xilinx, Inc. 1.2 rev 1 ISE 11.5 support
09/16/2009 Xilinx, Inc. 1.2 ISE 11.3 support
06/24/2009 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
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safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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