RISC_CPU
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1811KB
下载次数：3
上传日期：2015-12-19 12:05:29
上 传 者：
kangerdong1
说明： 毕业设计，基于Xilinx Spartan6自制开发板实验。毕业设计，能够实现简单的计算器。VHDDL
(Graduation design, development board based on Xilinx Spartan6 homemade experiment. Graduation design, to achieve a simple calculator. VHDDL)
文件列表:
RISC_CPU (0, 2015-12-15)
RISC_CPU\RTL (0, 2015-12-15)
RISC_CPU\RTL\ALU.vhd (2910, 2015-05-12)
RISC_CPU\RTL\CPU.vhd (14604, 2015-05-07)
RISC_CPU\RTL\DEC.vhd (29720, 2015-05-21)
RISC_CPU\RTL\EXE_reg.vhd (2219, 2015-04-20)
RISC_CPU\RTL\ID_reg.vhd (2783, 2015-04-20)
RISC_CPU\RTL\IF_reg.vhd (1506, 2015-04-21)
RISC_CPU\RTL\MEM_reg.vhd (1347, 2015-04-20)
RISC_CPU\RTL\RAM.vhd (1550, 2015-05-12)
RISC_CPU\RTL\ROM.vhd (23084, 2015-05-21)
RISC_CPU\RTL\Stack.vhd (1792, 2015-05-04)
RISC_CPU\RTL\control.vhd (1499, 2015-04-20)
RISC_CPU\RTL\fre_div.vhd (627, 2015-05-14)
RISC_CPU\RTL\gpr.vhd (1405, 2015-03-29)
RISC_CPU\RTL\mux_2_1.vhd (429, 2015-04-19)
RISC_CPU\RTL\ps2.vhd (5384, 2015-05-14)
RISC_CPU\RTL\top.vhd (2532, 2015-05-16)
RISC_CPU\UCF (0, 2015-12-15)
RISC_CPU\UCF\top.ucf (602, 2015-05-12)
RISC_CPU\risc (0, 2015-12-15)
RISC_CPU\risc\RISC.gise (12162, 2015-06-01)
RISC_CPU\risc\RISC.xise (38632, 2015-06-01)
RISC_CPU\risc\_ngo (0, 2015-12-15)
RISC_CPU\risc\_ngo\netlist.lst (54, 2015-06-01)
RISC_CPU\risc\_xmsgs (0, 2015-12-15)
RISC_CPU\risc\_xmsgs\bitgen.xmsgs (1775, 2015-06-01)
RISC_CPU\risc\_xmsgs\map.xmsgs (2862, 2015-06-01)
RISC_CPU\risc\_xmsgs\ngdbuild.xmsgs (367, 2015-06-01)
RISC_CPU\risc\_xmsgs\par.xmsgs (1568, 2015-06-01)
RISC_CPU\risc\_xmsgs\pn_parser.xmsgs (573, 2015-06-01)
RISC_CPU\risc\_xmsgs\trce.xmsgs (1024, 2015-06-01)
RISC_CPU\risc\_xmsgs\xst.xmsgs (82886, 2015-06-01)
RISC_CPU\risc\iseconfig (0, 2015-12-15)
RISC_CPU\risc\iseconfig\RISC.projectmgr (5035, 2015-06-01)
RISC_CPU\risc\iseconfig\top.xreport (20306, 2015-05-22)
RISC_CPU\risc\par_usage_statistics.html (4149, 2015-06-01)
RISC_CPU\risc\top.bgn (7657, 2015-06-01)
RISC_CPU\risc\top.bit (340692, 2015-06-01)
RISC_CPU\risc\top.bld (1048, 2015-06-01)
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