risc8_cpu_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：611KB
下载次数：2
上传日期：2015-12-24 16:13:18
上 传 者：
alvinr
说明： 该实例设计的RSIC-CPU总线结构采用数据线（8位）和指令线（12位）独立分离的哈弗结构，把存储寄存器RAM当做寄存器来寻址使用以方便编程。
(The example design of RISC-CPU bus architecture uses a data line (8) and command line (12) is separated with the Harvard architecture, the storage register addressing uses RAM as a register to facilitate programming.)
文件列表:
risc8 (0, 2015-11-17)
risc8\alu.v (1401, 2007-08-20)
risc8\basic.rom (2287, 1999-12-07)
risc8\chart (0, 2015-11-17)
risc8\chart\Thumbs.db (32256, 2007-12-24)
risc8\chart\ͼ13-11.bmp (455574, 2007-08-20)
risc8\chart\ͼ13-13.bmp (375786, 2007-08-20)
risc8\chart\ͼ13-15.bmp (278622, 2007-08-20)
risc8\chart\ͼ13-16.bmp (278622, 2007-08-20)
risc8\chart\ͼ13-17.bmp (366222, 2007-08-20)
risc8\chart\ͼ13-18.bmp (411774, 2007-08-20)
risc8\chart\ͼ13-20.bmp (630774, 2007-08-20)
risc8\chart\ͼ13-6.bmp (366222, 2007-08-20)
risc8\chart\ͼ13-7.bmp (366222, 2007-08-20)
risc8\chart\ͼ13-9.bmp (455574, 2007-08-20)
risc8\chart\表13-1.bmp (443286, 2007-08-20)
risc8\cpu.v (15821, 2007-08-20)
risc8\cpu_test.v (13104, 2007-08-20)
risc8\dram.v (331, 2007-08-23)
risc8\exp.v (1847, 2007-08-23)
risc8\idec.v (4379, 2007-08-20)
risc8\pram.v (460, 2007-08-23)
risc8\regs.v (1523, 2007-08-23)
risc8\risc8.cr.mti (1765, 2007-08-23)
risc8\risc8.mpf (18854, 2007-08-23)
risc8\risc8.vcd (1227307, 2007-08-20)
risc8\sindata.hex (8193, 1999-12-08)
risc8\transcript (338, 2007-08-23)
risc8\vsim.wlf (81920, 2007-08-20)
risc8\wave (0, 2015-11-17)
risc8\wave\Thumbs.db (24576, 2007-12-24)
risc8\wave\alu.bmp (1032954, 2007-08-20)
risc8\wave\cpu-1.bmp (2709354, 2007-08-20)
risc8\wave\cpu-2.bmp (2435454, 2007-08-20)
risc8\wave\cpu_test.bmp (1666554, 2007-08-20)
risc8\wave\exp.bmp (1257354, 2007-08-20)
risc8\wave\idec.bmp (1247454, 2007-08-20)
risc8\wave\pram.bmp (910854, 2007-08-20)
risc8\wave\regs.bmp (1067958, 2007-08-20)
risc8\work (0, 2015-11-17)
... ...
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