qnr_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：813KB
下载次数：2
上传日期：2015-12-24 16:28:57
上 传 者：
alvinr
说明： 量化取整QNR内部主要包括一个divider模块及产生数据输出有效和循环结果到最近整数的电路，包含仿真结果图。
(Rounding quantization internal QNR includes a divider module and generates data output valid and circulating the results to the nearest integer circuit, including the simulation results shown in Fig.)
文件列表:
10.4 (0, 2015-11-17)
10.4\bench_div_top.v (1828, 2007-08-21)
10.4\bench_qnr_top.v (2030, 2007-08-21)
10.4\chart (0, 2015-11-17)
10.4\chart\Thumbs.db (26112, 2007-12-24)
10.4\chart\ͼ10-32.bmp (430782, 2007-08-21)
10.4\chart\ͼ10-34.bmp (499374, 2007-08-21)
10.4\chart\ͼ10-35.bmp (586974, 2007-08-21)
10.4\chart\ͼ10-38.bmp (368882, 2007-08-21)
10.4\chart\ͼ10-39.bmp (345826, 2007-08-21)
10.4\chart\表10-4.bmp (308706, 2007-08-21)
10.4\chart\表10-5.bmp (315114, 2007-08-21)
10.4\div_su.v (1432, 2007-08-21)
10.4\div_uu.v (2578, 2007-08-21)
10.4\jpeg_qnr.v (1892, 2007-08-21)
10.4\qnr.cr.mti (1397, 2007-08-21)
10.4\qnr.mpf (18183, 2007-08-21)
10.4\timescale.v (21, 2007-08-21)
10.4\transcript (762564, 2007-08-21)
10.4\vsim.wlf (630784, 2007-08-21)
10.4\wave (0, 2015-11-17)
10.4\wave\Thumbs.db (14848, 2007-12-24)
10.4\wave\bench_qnr_top.bmp (1101546, 2007-08-21)
10.4\wave\chk_val.bmp (1165158, 2007-08-21)
10.4\wave\div_su.bmp (1496610, 2007-08-21)
10.4\wave\div_uu.bmp (1386126, 2007-08-21)
10.4\wave\jpeg_qnr.bmp (1493262, 2007-08-21)
10.4\work (0, 2015-11-17)
10.4\work\_info (1132, 2007-08-21)
10.4\work\bench_div_top (0, 2015-11-17)
10.4\work\bench_div_top\_primary.dat (2070, 2007-08-21)
10.4\work\bench_div_top\_primary.vhd (265, 2007-08-21)
10.4\work\bench_div_top\verilog.asm (37991, 2007-08-21)
10.4\work\bench_qnr_top (0, 2015-11-17)
10.4\work\bench_qnr_top\_primary.dat (1099, 2007-08-21)
10.4\work\bench_qnr_top\_primary.vhd (86, 2007-08-21)
10.4\work\bench_qnr_top\verilog.asm (10400, 2007-08-21)
10.4\work\chk_val (0, 2015-11-17)
10.4\work\chk_val\_primary.dat (1254, 2007-08-21)
10.4\work\chk_val\_primary.vhd (341, 2007-08-21)
... ...
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