Uart_to_bus
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：263KB
下载次数：2
上传日期：2015-12-29 06:01:30
上 传 者：
azimi
说明： The UART to Bus IP Core is a simple command parser that can be used to access an internal bus via a UART interface. The parser supports two modes of operation: text mode commands and binary mode commands. Text mode commands are designed to be used with a hyper terminal software and enable easy access to the internal bus. Binary mode commands are more efficient and also support buffered read & write operations with or without automatic address increment.
文件列表:
Uart_to_bus (0, 2015-12-31)
Uart_to_bus\uart2bus (0, 2015-12-31)
Uart_to_bus\uart2bus\branches (0, 2015-12-31)
Uart_to_bus\uart2bus\tags (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\doc (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\doc\UART to Bus Core Specifications.pdf (226688, 2012-02-25)
Uart_to_bus\uart2bus\trunk\scilab (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\scilab\calc_baud_gen.sce (1682, 2011-03-25)
Uart_to_bus\uart2bus\trunk\verilog (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\bench (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\bench\reg_file_model.v (2100, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\bench\tb_bin_uart2bus_top.v (6758, 2012-02-25)
Uart_to_bus\uart2bus\trunk\verilog\bench\tb_txt_uart2bus_top.v (5432, 2012-02-25)
Uart_to_bus\uart2bus\trunk\verilog\bench\tb_uart2bus_top.v (5613, 2012-02-25)
Uart_to_bus\uart2bus\trunk\verilog\bench\timescale.v (242, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\bench\uart_tasks.v (7706, 2012-02-25)
Uart_to_bus\uart2bus\trunk\verilog\rtl (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\rtl\baud_gen.v (1851, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\rtl\uart2bus_top.v (3150, 2012-02-25)
Uart_to_bus\uart2bus\trunk\verilog\rtl\uart_parser.v (20430, 2012-02-25)
Uart_to_bus\uart2bus\trunk\verilog\rtl\uart_rx.v (3217, 2011-11-22)
Uart_to_bus\uart2bus\trunk\verilog\rtl\uart_top.v (2229, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\rtl\uart_tx.v (2618, 2011-11-22)
Uart_to_bus\uart2bus\trunk\verilog\sim (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\block_bin.cfg (223, 2010-04-03)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\block_txt.cfg (223, 2010-04-03)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\compile_bin.bat (38, 2010-04-03)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\compile_txt.bat (38, 2010-04-03)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\gtk.bat (30, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\run.bat (27, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\test.bin (28, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\sim\icarus\test.txt (46, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\syn (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\syn\altera (0, 2015-12-31)
Uart_to_bus\uart2bus\trunk\verilog\syn\altera\uart2bus.qpf (1288, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\syn\altera\uart2bus.qws (90, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\syn\altera\uart2bus_top.qsf (3281, 2010-02-15)
Uart_to_bus\uart2bus\trunk\verilog\syn\xilinx (0, 2015-12-31)
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