example3
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：26KB
下载次数：4
上传日期：2011-03-11 11:32:21
上 传 者：
y314992140
说明： 加/减法计数器：本程序实现的是一个加/减8进制计数器
(Add/down counter: The program implementation is a plus/minus 8 binary counter)
文件列表:
example3\counter.asm.rpt (6525, 2007-09-04)
example3\counter.cdf (305, 2007-09-04)
example3\counter.done (26, 2007-09-04)
example3\counter.dpf (239, 2007-10-06)
example3\counter.fit.rpt (51513, 2007-09-04)
example3\counter.fit.smsg (334, 2007-09-04)
example3\counter.fit.summary (363, 2007-09-04)
example3\counter.flow.rpt (3909, 2007-09-04)
example3\counter.map.rpt (16605, 2007-09-04)
example3\counter.map.summary (290, 2007-09-04)
example3\counter.pin (14721, 2007-09-04)
example3\counter.pof (7855, 2007-09-04)
example3\counter.qpf (907, 2007-09-04)
example3\counter.qsf (1989, 2007-09-04)
example3\counter.qws (634, 2007-10-06)
example3\counter.tan.rpt (64196, 2007-09-04)
example3\counter.tan.summary (1616, 2007-09-04)
example3\counter.vhd (1409, 2007-10-19)
example3\实验说明.txt (587, 2007-10-06)
example3\db (0, 2011-01-30)
example3 (0, 2011-01-30)
近期下载者：
相关文件：
收藏者：