vga_test
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6957KB
下载次数：5
上传日期：2016-01-14 23:29:39
上 传 者：
jayash
说明： 基于nios的vga控制器,分辨率及显示区域,显示位数,显存深度可调整,已经在altera cyclone ii条件下测试通过 quartus13.0开发环境 主机端符合avalon标准
(VGA controller based on NIOS, resolution and display area show the median, the memory depth can be adjusted, has been in Altera cyclone II under the condition of test through the end of the quartus13.0 development environment of the host with Avalon standard)
文件列表:
vga_test\.qsys_edit\filters.xml (69, 2016-01-11)
vga_test\.qsys_edit\preferences.xml (745, 2016-01-14)
vga_test\db\add_sub_8ri.tdf (1574, 2016-01-12)
vga_test\db\altera_mult_add_mpt2.v (15690, 2016-01-12)
vga_test\db\altera_mult_add_opt2.v (15690, 2016-01-12)
vga_test\db\altsyncram_0bc1.tdf (8081, 2016-01-11)
vga_test\db\altsyncram_0ff1.tdf (41188, 2016-01-14)
vga_test\db\altsyncram_2q14.tdf (3695, 2016-01-13)
vga_test\db\altsyncram_3q14.tdf (3686, 2016-01-14)
vga_test\db\altsyncram_4bc1.tdf (13527, 2016-01-14)
vga_test\db\altsyncram_4q14.tdf (3696, 2016-01-13)
vga_test\db\altsyncram_5q14.tdf (3687, 2016-01-14)
vga_test\db\altsyncram_6ec1.tdf (33264, 2016-01-12)
vga_test\db\altsyncram_9tl1.tdf (12663, 2016-01-12)
vga_test\db\altsyncram_9vc1.tdf (38140, 2016-01-14)
vga_test\db\altsyncram_aeq1.tdf (55517, 2016-01-13)
vga_test\db\altsyncram_beq1.tdf (45077, 2016-01-14)
vga_test\db\altsyncram_ceq1.tdf (56677, 2016-01-13)
vga_test\db\altsyncram_deq1.tdf (46237, 2016-01-14)
vga_test\db\altsyncram_gef1.tdf (41181, 2016-01-14)
vga_test\db\altsyncram_gp14.tdf (15986, 2016-01-13)
vga_test\db\altsyncram_hk71.tdf (29582, 2016-01-12)
vga_test\db\altsyncram_idg1.tdf (21419, 2016-01-14)
vga_test\db\altsyncram_lmu.tdf (2695, 2016-01-11)
vga_test\db\altsyncram_m3g1.tdf (40841, 2016-01-12)
vga_test\db\altsyncram_mdg1.tdf (20265, 2016-01-14)
vga_test\db\altsyncram_mlg1.tdf (6468, 2016-01-12)
vga_test\db\altsyncram_mp14.tdf (3662, 2016-01-14)
vga_test\db\altsyncram_n3g1.tdf (40841, 2016-01-12)
vga_test\db\altsyncram_pmu.tdf (2707, 2016-01-14)
vga_test\db\altsyncram_qed1.tdf (38789, 2016-01-12)
vga_test\db\altsyncram_r1h1.tdf (28350, 2016-01-12)
vga_test\db\altsyncram_rpu.tdf (2712, 2016-01-12)
vga_test\db\altsyncram_udq1.tdf (17237, 2016-01-14)
vga_test\db\alt_synch_pipe_iv7.tdf (2048, 2016-01-11)
vga_test\db\alt_synch_pipe_jv7.tdf (2048, 2016-01-11)
vga_test\db\alt_synch_pipe_kv7.tdf (2044, 2016-01-12)
vga_test\db\alt_synch_pipe_lv7.tdf (2048, 2016-01-12)
vga_test\db\alt_synch_pipe_mv7.tdf (2048, 2016-01-14)
vga_test\db\alt_synch_pipe_nv7.tdf (2048, 2016-01-14)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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