uart
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：270KB
下载次数：2
上传日期：2016-01-17 22:10:17
上 传 者：
liukai1992
说明： 本例程是用verilog硬件描述语言在quaryusII环境下开发的串口通信模块，分为发送模块，接受模块和波特率产生模块。
(This routine is verilog hardware description language development environment under quartus II serial communication module, divided into send module, receive module and baud rate generator module.)
文件列表:
uart\db\logic_util_heursitic.dat (3608, 2016-01-14)
uart\db\my_uart_top.(0).cnf.cdb (1389, 2016-01-14)
uart\db\my_uart_top.(0).cnf.hdb (931, 2016-01-14)
uart\db\my_uart_top.(1).cnf.cdb (2949, 2016-01-14)
uart\db\my_uart_top.(1).cnf.hdb (1936, 2016-01-14)
uart\db\my_uart_top.(2).cnf.cdb (5423, 2016-01-14)
uart\db\my_uart_top.(2).cnf.hdb (1166, 2016-01-14)
uart\db\my_uart_top.(3).cnf.cdb (3111, 2016-01-14)
uart\db\my_uart_top.(3).cnf.hdb (1076, 2016-01-14)
uart\db\my_uart_top.asm.qmsg (2238, 2016-01-14)
uart\db\my_uart_top.asm.rdb (1288, 2016-01-14)
uart\db\my_uart_top.asm_labs.ddb (1866, 2016-01-14)
uart\db\my_uart_top.cbx.xml (93, 2016-01-14)
uart\db\my_uart_top.cmp.cdb (19748, 2016-01-14)
uart\db\my_uart_top.cmp.hdb (10561, 2016-01-14)
uart\db\my_uart_top.cmp.kpt (203, 2016-01-14)
uart\db\my_uart_top.cmp.logdb (4, 2016-01-14)
uart\db\my_uart_top.cmp.rdb (15805, 2016-01-14)
uart\db\my_uart_top.cmp.tdb (15295, 2016-01-14)
uart\db\my_uart_top.cmp0.ddb (40375, 2016-01-14)
uart\db\my_uart_top.db_info (137, 2016-01-14)
uart\db\my_uart_top.eco.cdb (161, 2016-01-14)
uart\db\my_uart_top.fit.qmsg (14585, 2016-01-14)
uart\db\my_uart_top.hier_info (6394, 2016-01-14)
uart\db\my_uart_top.hif (2834, 2016-01-14)
uart\db\my_uart_top.lpc.html (1598, 2016-01-14)
uart\db\my_uart_top.lpc.rdb (482, 2016-01-14)
uart\db\my_uart_top.lpc.txt (1935, 2016-01-14)
uart\db\my_uart_top.map.cdb (7244, 2016-01-14)
uart\db\my_uart_top.map.hdb (10421, 2016-01-14)
uart\db\my_uart_top.map.logdb (4, 2016-01-14)
uart\db\my_uart_top.map.qmsg (14026, 2016-01-14)
uart\db\my_uart_top.pre_map.cdb (7883, 2016-01-14)
uart\db\my_uart_top.pre_map.hdb (9984, 2016-01-14)
uart\db\my_uart_top.rpp.qmsg (1863, 2016-01-14)
uart\db\my_uart_top.rtlv.hdb (9959, 2016-01-14)
uart\db\my_uart_top.rtlv_sg.cdb (8380, 2016-01-14)
uart\db\my_uart_top.rtlv_sg_swap.cdb (936, 2016-01-14)
uart\db\my_uart_top.sgate.rvd (7916, 2016-01-14)
uart\db\my_uart_top.sgate_sm.rvd (220, 2016-01-14)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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