Interleaver_Deinterleaver
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：9KB
下载次数：53
上传日期：2016-01-21 12:14:10
上 传 者：
ranbowang
说明： 通信中卷积交织/解交织FPGA源程序，采用verilogHDL代码实现，包含测试程序，经过验证。
(Communication in the convolutional interleaving/de interleaving FPGA source program, using verilogHDL code to achieve, including test procedures, after verification.)
文件列表:
Interleaver_Deinterleaver (0, 2016-01-21)
Interleaver_Deinterleaver\resource (0, 2016-01-21)
Interleaver_Deinterleaver\resource\Convolutional_Deinterleaver.v (10084, 2011-07-08)
Interleaver_Deinterleaver\resource\Convolutional_Interleaver.v (9764, 2011-07-08)
Interleaver_Deinterleaver\resource\deinterleaver_channel_cont.v (1180, 2007-08-29)
Interleaver_Deinterleaver\resource\double_port_ram.v (888, 2007-08-28)
Interleaver_Deinterleaver\resource\interleaver_channel_cont.v (1110, 2007-08-29)
Interleaver_Deinterleaver\resource\Interleaver_Deinterleaver.v (3019, 2011-07-08)
Interleaver_Deinterleaver\resource\Interleaver_Deinterleaver_Testbench.v (2873, 2011-07-08)
卷积交织通用模块：
Convolutional_Interleaver.v为主模块，interleaver_channel_cont.v和double_port_ram.v为子模块
interleaver_channel_cont.v为分支通道递增计数模块，double_port_ram.v为双口RAM模块
卷积解交织通用模块：
卷积解交织是卷积交织的逆运算，主要的区别是交织时，主计数器main_counter递增，解交织时递减
Convolutional_Deinterleaver.v为主模块，deinterleaver_channel_cont.v和double_port_ram.v为子模块
deinterleaver_channel_cont.v为分支通道递增计数模块，double_port_ram.v为双口RAM模块
Interleaver_Deinterleaver_Testbench.v为顶层测试程序
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