文件列表:

xapp592_ver2_1\bit_files (0, 2014-07-24)
xapp592_ver2_1\bit_files\kc705_sdi_demo.bit (11443708, 2014-07-22)
xapp592_ver2_1\bit_files\kc705_sdi_pass.bit (11443708, 2014-07-22)
xapp592_ver2_1\chipscope_projects (0, 2014-07-24)
xapp592_ver2_1\chipscope_projects\kc705_sdi_demo.cpj (373437, 2014-02-06)
xapp592_ver2_1\chipscope_projects\kc705_sdi_pass.cpj (86688, 2014-02-07)
xapp592_ver2_1\dru (0, 2014-07-24)
xapp592_ver2_1\dru\dru.ngc (535702, 2013-01-03)
xapp592_ver2_1\dru\dru.v (4114, 2014-03-13)
xapp592_ver2_1\dru\dru_bshift10to10.v (5016, 2014-03-13)
xapp592_ver2_1\dru\dru_control.v (4403, 2014-03-13)
xapp592_ver2_1\dru\dru_maskencoder.v (4873, 2014-03-13)
xapp592_ver2_1\dru\dru_rot20.v (3952, 2014-03-13)
xapp592_ver2_1\dru\for_simulation_only (0, 2014-07-24)
xapp592_ver2_1\dru\for_simulation_only\dru_sim.v (4940, 2014-03-13)
xapp592_ver2_1\k7gtx_sdi_wrapper (0, 2014-07-24)
xapp592_ver2_1\k7gtx_sdi_wrapper\k7gtx_sdi_wrapper_common.v (10095, 2014-07-09)
xapp592_ver2_1\k7gtx_sdi_wrapper\k7gtx_sdi_wrapper_gt.v (46262, 2014-07-10)
xapp592_ver2_1\k7gtx_sdi_wrapper\k7gtx_sdi_wrapper_sync_block.v (4732, 2014-07-09)
xapp592_ver2_1\kc705_sdi_demo (0, 2014-07-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope (0, 2014-07-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\icon.ngc (151893, 2013-10-29)
xapp592_ver2_1\kc705_sdi_demo\chipscope\icon.v (1380, 2013-10-29)
xapp592_ver2_1\kc705_sdi_demo\chipscope\icon.xdc (793, 2013-10-29)
xapp592_ver2_1\kc705_sdi_demo\chipscope\rx_ila.ngc (557427, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\rx_ila.v (941, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\rx_ila.xdc (477, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\rx_vio.ngc (204634, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\rx_vio.v (988, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\rx_vio.xdc (69, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\tx_vio.ngc (56917, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\tx_vio.v (1030, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\tx_vio.xdc (69, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\vio0.ngc (27938, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\vio0.v (920, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\chipscope\vio0.xdc (80, 2013-10-24)
xapp592_ver2_1\kc705_sdi_demo\k7_sdi_rxtx.v (21687, 2014-03-13)
xapp592_ver2_1\kc705_sdi_demo\kc705_sdi_demo.v (21281, 2014-03-13)
xapp592_ver2_1\kc705_sdi_demo\kc705_sdi_demo.xdc (5752, 2014-03-13)
xapp592_ver2_1\kc705_sdi_demo\kc705_sdi_demo_timing.xdc (1932, 2014-03-13)
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************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2012 - 2014 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx Current readme.txt Version: 2.1 Date Last Modified: 24JUL2014 Date Created: 09AUG2012 Associated Filename: xapp592.zip Associated Document: XAPP592, Implementing SMPTE SDI Interfaces with Kintex-7 GTX Transceivers Supported Device(s): Kintex-7 FPGAs ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This readme file contains these sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. OTHER INFORMATION 7. SUPPORT 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 09AUG2012 1.0 Initial Xilinx release. 16OCT2012 1.1 Fixed typos in readme.txt file only. No changes to any other files. 17DEC2012 1.2 Made changes to the DRP controller in the SDI wrapper to insure that it correctly writes to the GTX through the DRP to change the RXCDR_CFG attribute dynamically. Created new GTX wrappers for the demos using v2.4 of the GTX wizard. Version 2.4 of the GTX wizard produces GTX wrappers with a slightly different set of ports, so the demos were updated to match the new GTX wrappers. 10JUL2014 2.0 The GTX wrappers generated by versions 3.0 and later of the transceiver wizard differ in very fundamental ways from wrappers created by earlier versions of the wizard. The SD/HD/3G-SDI core version 3.0 also has some port name changes from earlier versions of the core as required to comply with port naming standards for Xilinx IP. The SDI wrapper files have been updated to support these changes and to align the control logic and wrappers with the GTP and GTH SDI wrappers. All demo files have been updated to match these changes. VHDL versions of wrappers and demos have been removed. And, the app note now targets Vivado only. The code supplied here is compatible with Version 3.3 of the 7 Series FPGAs Transceivers Wizard that ships in Vivado 2014.2. 24JUL2014 2.1 With current Vivado synthesis, the ST 352 payload ID state machine in the SDI RX is susceptible to becoming stuck in an invalid state while the GTX RX is changing between SDI modes. The SDI wrapper has been modified to reset the SDI RX while the GTX RX is changing modes. ========================================================================= 2. OVERVIEW This readme describes how to use the files that come with XAPP592. There are two example SDI designs provided with XAPP592. One design has four SDI receivers and four SDI transmitters. The receivers and transmitters are all independent of each other. The SDI transmitters are driven by video pattern generators. The data received by the SDI receivers is captured by ChipScope Pro modules. The other design is a single channel SDI pass-through configuration where the SDI transmitter retransmits the signal received by the SDI receiver. 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS * Vivado 2013.4 or newer 4. DESIGN FILE HIERARCHY The directory structure underneath this top-level folder is described below: \bit_files | This folder contains FPGA configuration bit files for the demos included | in this release. | \chipscope_projects | This folder contains project files for ChipScope Pro analyzer, | one .cpj file for each of the demos included in this release. | \dru | This directory contains the data recovery unit (DRU) code required | to receive 270 Mb/s SD-SDI. The dru.ngc file contains the pre- | synthesized DRU IP. It must be added to the Vivado project along with | the HDL files in the \dru directory. | +--\for_simulation_only | This directory contains a simple model of the DRU that can be | used for simulation. The dru.ngc file cannot be simulated due to | encryption of the file. The simulation model must not, however, | be used in an actual FPGA configuration because it does not have | any jitter tolerance. | \k7gtx_sdi_wrapper | This directory contains the GTX wrapper and GTXE2_COMMON wrapper files | generated by the GTX wizard specifically for these demos. | \kc705_sdi_demo | This directory contains the HDL and other files unique to the quad | SDI demo. | \kc705_sdi_pass_demo | This directory contains the HDL and other files unique to the SDI | pass-through demo. | \kc705_TEDSDI_control | This directory contains the HDL and other files that are used by | both demos to control devices on the KC705 and the inrevium FMC boards. | \SDI_wrapper | This directory contains the HDL code for the SDI wrapper and its | various submodules. The HDL files in this directory is used by both | demos. And, these HDL files should be used in all custom SDI | applications using Kintex-7 GTX transceivers to interface the SMPTE | SDI core to the Kintex-7 GTX transceivers. 5. INSTALLATION AND OPERATING INSTRUCTIONS Instructions for running the demos from the provided bit files are provided in application note. The instructions below describe how to build the demos from the supplied Verilog source code. When using Vivado to create the SDI demos, you have the choice of using either ChipScope or Vivado Analyzer to control and monitor the demos. ChipScope is recommended because, at this time, it provides a better user interface. In the top level file of both demos there is a parameter named USE_CHIPSCOPE defined. If this parameter's value is "TRUE", ChipScope modules will be included into the project. If the parameter's value is anything else, Vivado Analyzer modules will be included. Vivado 2013.3 and later doesn't have native support for ChipScope. But, ChipScope can be used by generating the ChipScope modules in ISE and then including the necessary files into the Vivado project. Pregenerated ChipScope modules are included with these demos so you don't have to generate the ChipScope modules, just include the correct files. Instructions are provided for generating the demos using Vivado with both ChipScope and Vivado Analyzer. To use ChipScope with these demos, ChipScope Pro analyzer needs to be installed on the computer that will be connected to the KC705 board. You can download the free ISE 14.7 Lab Tools installation from the Xilinx web site to install ChipScope Pro Analyzer. -------------------------------------------------------------------------------- To build the Quad SDI demo (kc705_sdi_demo) with Vivado: 1) Launch Vivado and select Create New Project to launch the new project wizard. 2) On the Project Type screen, select RTL Project. 3) On the Add Sources screen: Add all of the .v files from the kc705_sdi_demo directory. If you are using ChipScope to control & monitor the demo, add all of the .v and .ngc files from the kc705_sdi_demo/chipscope directory. Add all of the .v files from the k7gtx_sdi_wrapper directory. Add all of the .v files from the SDI_wrapper directory. Add all of the .v files from the kc705_TEDSDI_control directory. Add the k7_sdi_demo_name.txt from the kc705_TEDSDI_control directory. Note that you will have to change the "Files of type:" setting to "All Files" to see the .txt file. Add all of the .v files and the dru.ngc file from the dru directory. (Do not include the files in the dru/for_simulation_only directory. 4) Click Next to move to the Add Existing IP screen (do not add any existing IP) and then Next again to move to the Add Constraints screen. The following files should automatically have been added to your project. If they are not there, add them from the vc709_sdi_pass_demo and the vc709_sdi_demo/chipscope directories. kc705_sdi_demo_timing.xdc kc705_sdi_demo.xdc If using ChipScope, also include (again they will probably automatically be included): icon.xdc rx_vio.xdc rx_ila.xdc tx_vio.xdc vio0.xdc 5) Click Next to move the Default Part screen. When using the KC705 board, set the part to: xc7k325tffg900-2. 6) Click next to move to the summary page and then click Finish. 7) At the current time, portability of IP cores in Vivado is limited. Thus, the following instructions should be followed to create all of the IP cores needed by the demo from scratch using the IP Catalog. Open the IP Catalog either from Windows > IP Catalog in the tool bar at the top of the Vivado GUI or by clicking on IP Catalog under Project Manager in the Flow Navigator on the left side of the Vivado GUI. 7a) Generate a SMPTE SD/HD/3G-SDI core: In the IP Catalog window under the Video & Image Processing tab, locate the SMPTE SD/HD/3G-SDI core and double click on it. This will open the GUI for the SDI core. In the SDI core GUI, change the component name to: smpte_sdi. Make sure that the Include Rx EDH Processor option is selected. Click OK. If you are using ChipScope to control & monitor the demo, skip to step 8. If you are using Vivado Analyzer, do steps 7b to 7e. Don't forget to edit the kc705_sdi_demo.v file to change the value of the USE_CHIPSCOPE parameter to something other than "TRUE" if using Vivado Analyzer. 7b) Generate a Vivado Logic Analyzer VIO core: In the IP Catalog window under Debug & Verification > Debug, locate VIO and double click on it to launch the VIO customization window. Set the component name to vio0. The default name will be vio_0, so simply remove the underscore. In the General Options tab, set the Input Probe Count value to 5 and the Output Probe Count value to 0. In the PROBE_IN Ports(0..15) tab, the width of all PROBE_IN ports must be left at their default widths of 1. Click on the OK button to finish customizing the core and then, when it appears, click the Generate button. 7c) Generate a second Vivado Logic Analyzer VIO core: In the IP Catalog window under Debug & Verification > Debug, locate VIO and double click on it to launch the VIO customization window. Set the component name to tx_vio. In the General Options tab, set the Input Probe Count value to 3 and the Output Probe Count value to 5. In the PROBE_IN Ports(0..15) tab, set the PROBE_IN2 port width to 3 and leave all other port widths at their default width of 1. In the PROBE_OUT Ports(0..15) tab, set the various ports to these widths: PROBE_OUT0 = 1 PROBE_OUT1 = 1 PROBE_OUT2 = 3 PROBE_OUT3 = 2 PROBE_OUT4 = 2 It is also useful to set the Initial Value of the PROBE_OUT2 port to a value of 0x4. This defaults the video format to a format supported in all SDI modes. Click on the OK button to finish customizing the core and then, when it appears, click the Generate button. 7d) Generate a third Vivado Logic Analyzer VIO core: In the IP Catalog window under Debug & Verification > Debug, locate VIO and double click on it to launch the VIO customization window. Set the component name to rx_vio. In the General Options tab, set the Input Probe Count value to 16 and the Output Probe Count value to 2. In the PROBE_IN Ports(0..15) tab, set the PROBE_IN port widths to: PROBE_IN0 = 2 PROBE_IN1 = 1 PROBE_IN2 = 4 PROBE_IN3 = 1 PROBE_IN4 = 1 PROBE_IN5 = 32 PROBE_IN6 = 1 PROBE_IN7 = 1 PROBE_IN8 = 16 PROBE_IN9 = 4 PROBE_IN10 = 1 PROBE_IN11 = 1 PROBE_IN12 = 1 PROBE_IN13 = 1 PROBE_IN14 = 1 PROBE_IN15 = 3 In the PROBE_OUT Ports(0..15) tab, leave both PROBE_OUT ports at their default width of 1 bit. Click the OK button to finish customizing the core and then, when it appears, click the Generate button. 7e) Generate a Vivado Logic Analyzer ILA core: In the IP Catalog window under Debug & Verification > Debug, locate ILA and double click on it to launch the ILA customization GUI. Set the component name to rx_ila. On the General Options tab, set the Number of Probes to 10 and the Sample Data Depth to 16384. On the two Probe Ports tabs, set the width of the various ports to: PROBE0 = 1 PROBE1 = 1 PROBE2 = 1 PROBE3 = 11 PROBE4 = 10 PROBE5 = 10 PROBE6 = 10 PROBE7 = 10 PROBE8 = 1 PROBE9 = 1 Click the OK button to finish customizing the core and then, when it appears, click the Generate button. 8) If using ChipScope, change the properties of the five xdc constraint files that are associated with the five ChipScope cores. The easiest way to do this is to run the following Tcl commands from the Vivado Tcl Console. You can copy each command line from this file and paste them into the Tcl command line. set_property USED_IN_SYNTHESIS false [get_files {icon.xdc vio0.xdc tx_vio.xdc rx_vio.xdc rx_ila.xdc}] set_property SCOPED_TO_REF {vio0} [get_files vio0.xdc] set_property SCOPED_TO_REF {tx_vio} [get_files tx_vio.xdc] set_property SCOPED_TO_REF {rx_vio} [get_files rx_vio.xdc] set_property SCOPED_TO_REF {rx_ila} [get_files rx_ila.xdc] set_property SCOPED_TO_REF {icon} [get_files icon.xdc] 9) If any mistakes were made in setting the component names of any of the IP cores generated using IP Catalog, the IP cores with the component names that are incorrect will show up as extra sources in the Sources Hierarchy pane in Vivado. Delete any that are incorrect and generate them again using the instructions above. 10) Run Synthesis, Implementation, and Generate Bitfile to create a bit file for this demo. -------------------------------------------------------------------------------- To build the SDI pass-through demo (kc705_sdi_pass_demo) with Vivado: Vivado Verilog flow: 1) Launch Vivado and select Create New Project to launch the new project wizard. 2) On the Project Type screen, select RTL Project. 3) On the Add Sources screen: Add all of the .v files from the kc705_sdi_pass_demo directory. If you are using ChipScope to control & monitor the demo, Add all of the .v and .ngc files from the kc705_sdi_pass_demo/chipscope directory. Add all of the .v files from the k7gtx_sdi_wrapper directory. Add all of the .v files from the SDI_wrapper directory. Add all of the .v files from the kc705_TEDSDI_control directory. Add the k7_sdi_demo_name.txt from the kc705_TEDSDI_control directory. Note that you will have to change the "Files of type:" setting to "All Files" to see the .txt file. Add all of the .v files and the dru.ngc file from the verilog/dru directory. (Do not include the files in the dru/for_simulation_only directory. 4) Click Next to move to the Add Existing IP screen (do not add any existing IP) and then Next again to move to the Add Constraints screen. The following files should automatically have been added to your project. If they are not there, add them from the vc709_sdi_pass_demo and the vc709_sdi_demo/chipscope directories. kc705_sdi_pass_demo_timing.xdc vc709_sdi_pass_demo.xdc If using ChipScope, also include (again, they will probably already be included): icon.xdc ila.xdc rx_vio.xdc vio.xdc 5) Click Next to move the Default Part screen. When using the KC705 board, set the part to: xc7k325tffg900-2. 6) Click next to move to the summary page and then click Finish. 7) At the current time, portability of IP cores ... ...

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