UART_DPLL
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:33KB
下载次数:2
上传日期:2016-04-01 10:02:17
上 传 者:
王权富贵哈哈哈
说明: 通过串口uart rs232控制的全数字锁相环,dpll,
可锁时钟相位
(UART CTORLER DPLL MODULE CLK)
文件列表:
UART_DPLL\divfrequency32.v (398, 2008-03-21)
UART_DPLL\divfrequency32_tp.v (264, 2008-03-20)
UART_DPLL\divfrequency64.v (429, 2008-03-21)
UART_DPLL\divfrequency64_tp.v (266, 2008-03-20)
UART_DPLL\divfrequency8.v (364, 2008-03-21)
UART_DPLL\divfrequency8_tp.v (275, 2008-03-20)
UART_DPLL\dpll.v (1520, 2008-03-21)
UART_DPLL\dpll_tb.cr.mti (1150, 2016-03-31)
UART_DPLL\dpll_tb.mpf (93508, 2016-03-31)
UART_DPLL\dpll_tp.v (375, 2008-03-27)
UART_DPLL\maichongjiajian.v (3292, 2008-03-20)
UART_DPLL\maichongjiajian_tp.v (385, 2008-03-20)
UART_DPLL\moKcounter.v (2253, 2008-03-21)
UART_DPLL\moKcounter_tp.v (385, 2008-03-20)
UART_DPLL\vsim.wlf (73728, 2016-03-31)
UART_DPLL\xorphd.v (161, 2008-03-21)
UART_DPLL\xorphd_tp.v (249, 2008-03-21)
UART_DPLL (0, 2016-04-01)
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