DSSS
所属分类：VHDL/FPGA/Verilog
开发工具：matlab
文件大小：11135KB
下载次数：31
上传日期：2016-04-03 19:34:30
上 传 者：
会飞翔的鱼
说明： 用VHDL实现基于Xilinx的FPGA上的直接序列扩频通信，并且附带了matlab仿真程序。
(VHDL implementation based on direct sequence spread spectrum communication on Xilinx' s FPGA, and comes with matlab simulation program.)
文件列表:
Chapter_9 (0, 2016-03-07)
Chapter_9\E9_1 (0, 2016-03-07)
Chapter_9\E9_1\E9_1_DSSProduce.m (6002, 2016-02-29)
Chapter_9\E9_1\E9_1_PnCode.m (2004, 2016-02-29)
Chapter_9\E9_1\data_ads.txt (21080001, 2014-02-18)
Chapter_9\E9_1\dss.txt (12400001, 2014-02-18)
Chapter_9\E9_1\pncode.coe (1056, 2014-02-20)
Chapter_9\E9_1\rcos_ads.txt (21080001, 2014-02-18)
Chapter_9\E9_1\tra_lpf.coe (355, 2014-02-18)
Chapter_9\E9_2 (0, 2016-03-07)
Chapter_9\E9_2\DssMod (0, 2016-03-07)
Chapter_9\E9_2\DssMod\.recordref (0, 2013-12-30)
Chapter_9\E9_2\DssMod\DataPn.vhd (1455, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.cmd_log (1146, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.dhp (3552, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.gise (8073, 2014-02-20)
Chapter_9\E9_2\DssMod\DssMod.ise (72127, 2014-02-20)
Chapter_9\E9_2\DssMod\DssMod.ise_ISE_Backup (4490, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.lso (6, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.ngc (11426, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.ngr (12474, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.ntrc_log (116, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.prj (154, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.stx (0, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.syr (22999, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod.vhd (3531, 2014-01-05)
Chapter_9\E9_2\DssMod\DssMod.xise (43414, 2014-02-20)
Chapter_9\E9_2\DssMod\DssMod.xst (1101, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod_ise11migration.zip (72117, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod_summary.html (5273, 2014-02-20)
Chapter_9\E9_2\DssMod\DssMod_vhdl.prj (203, 2014-01-04)
Chapter_9\E9_2\DssMod\DssMod_xdb (0, 2016-03-07)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp (0, 2016-03-07)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise (0, 2016-03-07)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise\__OBJSTORE__ (0, 2016-03-07)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise\__OBJSTORE__\Autonym (0, 2016-04-03)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise\__OBJSTORE__\ConstraintSystem (0, 2016-04-03)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise\__OBJSTORE__\Cs (0, 2016-04-03)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign (0, 2016-03-07)
Chapter_9\E9_2\DssMod\DssMod_xdb\tmp\ise\__OBJSTORE__\HierarchicalDesign\HDProject (0, 2016-03-07)
... ...
The following files were generated for 'nco' in directory
D:\ModemPrograms\Chapter_9\E9_2\DssMod\ipcore_dir\
nco_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
nco.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
nco.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
nco.ise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
nco.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
nco.sym:
Please see the core data sheet.
nco.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
nco.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
nco.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
nco.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
nco.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
nco.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
nco_readme.txt:
Text file indicating the files generated and how they are used.
nco_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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