UART
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：270KB
下载次数：320
上传日期：2011-03-18 22:09:19
上 传 者：
2401813
说明： FPGA的UART程序，非常好的，讲解详细，我当初看了好多都看不懂，看了这个以后终于明白
(FPGA' s UART program, very good, detailed explanation, I had read a lot have not read, finally realized after reading this)
文件列表:
UART (0, 2008-10-25)
UART\component (0, 2008-10-25)
UART\constraint (0, 2008-10-25)
UART\coreconsole (0, 2008-10-25)
UART\designer (0, 2008-10-25)
UART\designer\impl1 (0, 2008-10-25)
UART\designer\impl1\designer.log (529, 2007-11-13)
UART\designer\impl1\simulation (0, 2008-10-25)
UART\designer\impl1\uart_test.adb (169984, 2007-11-13)
UART\designer\impl1\uart_test.dtf (0, 2008-10-25)
UART\designer\impl1\uart_test.dtf\verify.log (233, 2007-04-16)
UART\designer\impl1\uart_test.ide_des (661, 2007-11-13)
UART\designer\impl1\uart_test.stp (49448, 2007-04-16)
UART\designer\impl1\uart_test.tcl (174, 2007-11-13)
UART\hdl (0, 2008-10-25)
UART\hdl\rec.v (2306, 2007-03-19)
UART\hdl\send.v (2054, 2007-03-19)
UART\hdl\uart_test.v (1407, 2007-04-16)
UART\phy_synthesis (0, 2008-10-25)
UART\simulation (0, 2008-10-25)
UART\simulation\meminit.dat (2816, 2007-11-13)
UART\simulation\modelsim.ini (235, 2007-11-13)
UART\simulation\modelsim.ini.sav (242, 2007-04-16)
UART\smartgen (0, 2008-10-25)
UART\smartgen\smartgen.aws (376, 2007-11-13)
UART\stimulus (0, 2008-10-25)
UART\synthesis (0, 2008-10-25)
UART\synthesis\stdout.log (688, 2007-04-16)
UART\synthesis\syntmp (0, 2008-10-25)
UART\synthesis\syntmp\sap.log (188, 2007-04-16)
UART\synthesis\syntmp\uart_test.msg (529, 2007-04-16)
UART\synthesis\syntmp\uart_test.plg (709, 2007-04-16)
UART\synthesis\traplog.tlg (3925, 2007-04-16)
UART\synthesis\uart_test.areasrr (5534, 2007-04-16)
UART\synthesis\uart_test.edn (140643, 2007-04-16)
UART\synthesis\uart_test.fse (0, 2007-03-19)
UART\synthesis\uart_test.map (0, 2007-04-16)
UART\synthesis\uart_test.sdf (94331, 2007-04-16)
UART\synthesis\uart_test.srd (58813, 2007-04-16)
UART\synthesis\uart_test.srm (279448, 2007-04-16)
... ...
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