uart
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2511KB
下载次数：27
上传日期：2016-04-13 19:08:19
上 传 者：
DZCK
说明： verilog 编写的FPGA串口报文收发程序，带奇偶校验位，并含有DS18B20温度传感器驱动程序，可以自行设置波特率.
(verilog prepared by the FPGA serial transceiver procedures packets with parity, and contains a temperature sensor DS18B20 driver, you can set the baud rate yourself.)
文件列表:
uart\11.wcfg (4650, 2016-01-19)
uart\debug.cdc (9117, 2016-01-20)
uart\fuse.log (2045, 2016-01-20)
uart\fuse.xmsgs (751, 2016-01-20)
uart\fuseRelaunch.cmd (253, 2016-01-20)
uart\ipcore_dir\coregen.cgp (237, 2016-01-19)
uart\ipcore_dir\coregen.log (186, 2016-01-20)
uart\ipcore_dir\create_pll_clock.tcl (1257, 2016-01-19)
uart\ipcore_dir\edit_pll_clock.tcl (1124, 2016-01-20)
uart\ipcore_dir\pll_clock\doc\clk_wiz_v3_6_vinfo.html (6789, 2016-01-19)
uart\ipcore_dir\pll_clock\doc\pg065_clk_wiz.pdf (42657, 2016-01-19)
uart\ipcore_dir\pll_clock\example_design\pll_clock_exdes.ucf (2623, 2016-01-19)
uart\ipcore_dir\pll_clock\example_design\pll_clock_exdes.v (5070, 2016-01-19)
uart\ipcore_dir\pll_clock\example_design\pll_clock_exdes.xdc (3115, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\implement.bat (3634, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\implement.sh (3513, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\planAhead_ise.bat (2695, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\planAhead_ise.sh (2603, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\planAhead_ise.tcl (3094, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\planAhead_rdn.bat (2690, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\planAhead_rdn.sh (2595, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\planAhead_rdn.tcl (3212, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\xst.prj (82, 2016-01-19)
uart\ipcore_dir\pll_clock\implement\xst.scr (173, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simcmds.tcl (145, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_isim.bat (2768, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_isim.sh (2651, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_mti.bat (2763, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_mti.do (2682, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_mti.sh (2633, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_ncsim.sh (2760, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\simulate_vcs.sh (2904, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\ucli_commands.key (100, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\vcs_session.tcl (955, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\wave.do (2813, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\functional\wave.sv (4145, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\pll_clock_tb.v (4858, 2016-01-19)
uart\ipcore_dir\pll_clock\simulation\timing\pll_clock_tb.v (5347, 2016-01-19)
... ...
The following files were generated for 'icon_pro' in directory
E:\project\RX_Project\other\uar\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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