文件列表:

cic-miso\DesignExample\CIC_MISO_v72\ciccomp.m (6058, 2011-03-10)
cic-miso\DesignExample\CIC_MISO_v72\fdcoeffR4N4M2L30.txt (651, 2011-03-09)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\cic_v7_2.vhd (8540, 2008-01-20)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\fir_compiler_v7_2.vhd (12092, 2008-01-20)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\alt_avalonst_pfc_0_fifo_out0.v (10434, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\alt_avalonst_pfc_0_fifo_out1.v (10434, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\alt_avalonst_pfc_0.v (25233, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0.v (25233, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0_fifo_out0.v (10434, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0_fifo_out1.v (10434, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.map.qmsg (30315, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.db_info (137, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.cbx.xml (642, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\altsyncram_4f11.tdf (40557, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\altsyncram_pvt.tdf (43597, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.hier_info (29194, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.lpc.txt (1696, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.lpc.html (1208, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.lpc.rdb (437, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.smart_action.txt (8, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.pre_map.hdb (19732, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.pre_map.cdb (21532, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\db\alt_avalonst_pfc_0.sld_design_entry_dsc.sci (200, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0.qpf (1274, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0.vho (192334, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0_simgen_gate.xml (44187, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\simgen_temp\alt_avalonst_pfc_0.qsf (2418, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\alt_avalonst_pfc_0.vho (192334, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.map.qmsg (29302, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.db_info (137, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.cbx.xml (642, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\altsyncram_4f11.tdf (40557, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\altsyncram_pvt.tdf (43597, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.hier_info (29194, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.lpc.txt (1696, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.lpc.html (1208, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.lpc.rdb (437, 2011-03-07)
cic-miso\DesignExample\CIC_MISO_v72\DSPBuilder_CICDownMISO_import\db\alt_avalonst_pfc_0.smart_action.txt (8, 2011-03-07)
... ...

CIC Decimation Filter with Multi-channel Data Support v7.2 README File This readme file contains the following sections: o Package Contents o Tool Requirements o General Description o Simulation in Simulink o Release History o Design Examples Disclaimer o Contacting Altera Package Contents ================ Altera CIC Decimation Filter with Multi-channel Data Support v6.1 Design Example Files in this zip download include: o CICDownMISO.mdl - DSP Builder design file for data rate down conversion o ciccomp.m - MATLAB script for designing an inverse Sinc CIC compensation filter o cic_v7_2.vhd - wrapper file to generate the Altera CIC Compiler IP core implementing decimation by 4 o fir_compiler_v7_2.vhd - wrapper file to generate the Altera FIR Compiler IP core implementing decimation by 2 o fdcoeffR4N2M2L30.txt - pre-generated compensating FIR filter coefficients Tool Requirements ================= This design example requires the following software package: o Quartus II 7.2 o DSP Builder v7.2 o CIC MegaCore v7.2 o FIR MegaCore v7.2 o MATLAB/Simulink (Version R2006a to R2007b are supported.) Please contact your local sales representative if you do not have one of these software tools. General Description ============================= This design example illustrates how to implement multi-channel data rate down conversion using Altera CIC Compiler in the MISO mode. The DSP Builder design implements overall decimation by 8 for two independent data sources, with CIC down sampling the data by 4 and a compensating FIR filter implementing additional decimation by 2. The CIC filter is configured to have multiple parallel interfaces (Multiple-input-singule-output mode) for resource re-use. The CIC filter is followed by a compensating FIR filter, which has an inverse-sinc frequency response. Altera Avalon Streaming Interface is adopted to transfer packet data from multiple sources between IP cores. A MATLAB script is provided to users for designing of the inverse Sinc compensating filter coefficients. Users can modify on this example to generate a multiple-interface, multiple-channels per interface configuration for the CIC filter. For examples of various multiple channel data rate conversion systems, please refer to Altera Application Notes 421 Accelerating WiMax DDC & DDC System Designs. Please use causion with under-utilized input channels and please refer to CIC Compiler v6.1 Errata Sheet (Dec 14, 2006) for the most up-to-date information on CIC Compiler. Simulation in Simulink ====================== To run the simulation of the design example in Simulink, perform the following steps: 1. Open the design file CICDownMISO.mdl 2. From MATLAB command line, type alt_dspbuilder_refresh_megacore. This will generate the simulation model for the megacores used in this design example. 3. To start simulation, select "Start" (Simulation menu) and run the simulation. Make sure the discrete solver is selected with fixed simulation steps. 4. Check the simulation inputs and outputs. The input sinusoidal waves sampled at 80Mhz are corrupted by high frequency noise after certain number of clock cycles. The output signal has reduced sample rate of 10Mhz but still keeps the sinusoidal waves characteritics. The high frequency noise is filtered out. The input inphase data spectrum has a spike at 2.5Mhz, corresponding to a sine wave with center frequency of 2.5Mhz. The output signal spectrum is kept intact at 2.5Mhz although the data rate is reduced. To get more details on the design flow using DSP Builder, refer to the DSP Builder User Guide located at: http://www.altera.com/literature/ug/ug_dsp_builder.pdf Release History =============== Version 7.2 ------------- v7.2 release Version 6.1 ------------- Initial release Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera. Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: http://www.altera.com http://www.altera.com/mysupport/ Technical Support Hotline: (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally) Copyright (c) 2007 Altera Corporation. All rights reserved.

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