uart_lvds
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：3749KB
下载次数：7
上传日期：2016-04-30 13:47:34
上 传 者：
nuaadot
说明： 在fpga平台上开发uart接口，使用verilog语言编写。
(fpga for uart based on verilog)
文件列表:
uart_lvds (0, 2013-12-14)
uart_lvds\_ngo (0, 2013-11-20)
uart_lvds\_ngo\netlist.lst (138, 2013-11-20)
uart_lvds\_xmsgs (0, 2013-11-20)
uart_lvds\_xmsgs\bitgen.xmsgs (29305, 2013-11-20)
uart_lvds\_xmsgs\map.xmsgs (34213, 2013-11-20)
uart_lvds\_xmsgs\ngdbuild.xmsgs (617, 2013-11-20)
uart_lvds\_xmsgs\par.xmsgs (17698, 2013-11-20)
uart_lvds\_xmsgs\pn_parser.xmsgs (926, 2013-12-14)
uart_lvds\_xmsgs\trce.xmsgs (1842, 2013-11-20)
uart_lvds\_xmsgs\xst.xmsgs (36472, 2013-11-20)
uart_lvds\clk_div.v (3179, 2013-11-20)
uart_lvds\clk_div_arwz.ucf (729, 2013-11-20)
uart_lvds\coregen.cgc (2049, 2013-12-03)
uart_lvds\coregen.cgp (518, 2013-12-03)
uart_lvds\dcm.v (3031, 2013-11-20)
uart_lvds\dcm_arwz.ucf (729, 2013-11-20)
uart_lvds\ipcore_dir (0, 2013-12-03)
uart_lvds\ipcore_dir\IP.cgc (4311, 2013-12-03)
uart_lvds\ipcore_dir\IP.cgp (523, 2013-12-03)
uart_lvds\ipcore_dir\_xmsgs (0, 2013-11-20)
uart_lvds\ipcore_dir\_xmsgs\netgen.xmsgs (665, 2013-11-20)
uart_lvds\ipcore_dir\_xmsgs\ngcbuild.xmsgs (367, 2013-11-20)
uart_lvds\ipcore_dir\_xmsgs\pn_parser.xmsgs (940, 2013-12-14)
uart_lvds\ipcore_dir\_xmsgs\xst.xmsgs (44198, 2013-11-20)
uart_lvds\ipcore_dir\clk_div.cgc (6800, 2013-11-20)
uart_lvds\ipcore_dir\clk_div.cgp (523, 2013-11-20)
uart_lvds\ipcore_dir\clk_div.v (3197, 2013-11-20)
uart_lvds\ipcore_dir\clk_div.xaw (3212, 2013-11-20)
uart_lvds\ipcore_dir\clk_div_arwz.ucf (729, 2013-11-20)
uart_lvds\ipcore_dir\clk_div_flist.txt (95, 2013-11-20)
uart_lvds\ipcore_dir\clk_div_xmdf.tcl (1684, 2013-11-20)
uart_lvds\ipcore_dir\coregen.cgc (40620, 2013-11-20)
uart_lvds\ipcore_dir\coregen.cgp (531, 2013-11-20)
uart_lvds\ipcore_dir\dcm.cgc (6772, 2013-11-20)
uart_lvds\ipcore_dir\dcm.v (3049, 2013-11-20)
uart_lvds\ipcore_dir\dcm.xaw (3042, 2013-11-20)
uart_lvds\ipcore_dir\dcm_arwz.ucf (729, 2013-11-20)
uart_lvds\ipcore_dir\dcm_flist.txt (79, 2013-11-20)
... ...
The following files were generated for 'ila' in directory
E:\uart_lvds\ipcore_dir\
ila.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
ila.cdc:
Please see the core data sheet.
ila.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ila.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
ila.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
ila.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
ila.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ila.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ila.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ila.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ila_readme.txt:
Text file indicating the files generated and how they are used.
ila_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
ila_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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