Simple-digital-clock-design

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:266KB
下载次数:5
上传日期:2016-05-16 16:12:36
上 传 者MQmanzhushahua
说明:  简单数字钟应该具有显示时-分-秒的功能。首先要知道钟表的工作机理,整个钟表的工作应该是在1Hz信号的作用下进行,这样每来一个时钟信号,秒增加1秒,当秒从59秒跳转到00秒时,分钟增加1分,同时当分钟从59分跳转。
(It should have a simple digital clock display- minutes- seconds function. We must first know the working mechanism of clocks, watches the entire work should be in the role of 1Hz signal is carried out so that each to a clock signal, second by 1 second, when the second jump 59 seconds to 00 seconds, minutes, 1-point increase while when the minutes 59 minutes to jump.)

文件列表:
Simple digital clock design.doc (397824, 2016-05-16)

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