文件列表:

Project\21_SPI_RC522\gd32f1x0_conf.h (1271, 2016-02-24)
Project\21_SPI_RC522\gd32f1x0_it.c (2250, 2016-06-08)
Project\21_SPI_RC522\gd32f1x0_it.h (1008, 2016-02-24)
Project\21_SPI_RC522\main.c (7463, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\list\Project.map (85198, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\list\startup_gd32f1x0.lst (53464, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_adc.crf (262852, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_adc.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_adc.o (287540, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_can.crf (123, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_can.d (83, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_can.o (4452, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_cec.crf (256918, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_cec.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_cec.o (260864, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_cmp.crf (256344, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_cmp.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_cmp.o (249944, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_crc.crf (256303, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_crc.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_crc.o (252460, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_dac.crf (257169, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_dac.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_dac.o (254948, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_dma.crf (257862, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_dma.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_dma.o (255380, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_eval.crf (260913, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_eval.d (2549, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_eval.o (254624, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_exti.crf (256686, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_exti.d (2579, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_exti.o (249072, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_fmc.crf (260616, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_fmc.d (2545, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_fmc.o (276212, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_gpio.crf (257297, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_gpio.d (2579, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_gpio.o (257904, 2016-06-08)
Project\21_SPI_RC522\MDK-ARM\output\gd32f1x0_i2c.crf (262324, 2016-06-08)
... ...

/** ****************************************************************************** * @file SPI/SPI_FullDuplex_CRC/readme.txt * @author MCU SD * @version V2.0.0 * @date 15-Jan-2016 * @brief Description of the SPI_FullDuplex_CRC example. ****************************************************************************** */ @brief This demo is based on the GD32150R-EVAL/ GD32190R-EVAL board,The function of this demo is exchange data between SPI1 and SPI2.SPI1 is set as master and SPI2 is slave.They are work in fullduplex mode and followed by CRC transmission. After the SPI1_Buffer_Tx and SPI2_Buffer_Tx are sent and SPI2_Buffer_Rx and SPI1_Buffer_Rx are received, check whether the SPI2_Buffer_Rx, SPI1_Buffer_Tx and SPI1_Buffer_Rx, SPI2_Buffer_Tx are the same. If the data received is equal to data sent, TransferStatus1 and TransferStatus2 are equal to PASSED. Then SPI1 and SPI2 CRC Error flags are checked, TransferStatus1 and TransferStatus2 are assigned to FAILED if one of the SPI_FLAG_CRCERR flags are equal to SET. @note Connect SPI1 SCK PIN(PA5) TO SPI2 SCK PIN(PB13) Connect SPI1 MISO PIN(PA6) TO SPI2 MISO PIN(PB14) Connect SPI1 MOSI PIN(PA7) TO SPI2 MOSI PIN(PB15) /****************** (C) COPYRIGHT 2016 GIGADEVICE *********END OF FILE*********/

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