srl2pal
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：18KB
下载次数：2
上传日期：2016-06-12 15:46:22
上 传 者：
GONGDAYIGE
说明： 数据流串并转换的实现方法多种多样，根据数据的排序和数量的要求，可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说，可以使用移位寄存器完成串并转换；对于排列顺序有规定的串并转换，可以用case语句判断实现；对于复杂的串并转换，还可以用状态机实现
(Serial data stream and converts a variety of implementations, according to the sort and quantity of data requirements, you can choose a shift register, RAM or the like. For the relatively small amount of data design, it can be completed using a shift register serial to parallel converter the order of the provisions of the serial to parallel converter can be used to achieve case statement to determine for complex serial to parallel conversion, you can use state machine)
文件列表:
串并转换建模\rev_1\AutoConstraint_srl2pal.sdc (172, 2006-01-11)
串并转换建模\rev_1\rpt_srl2pal.areasrr (2033, 2006-01-11)
串并转换建模\rev_1\rpt_srl2pal_areasrr.htm (2474, 2006-01-11)
串并转换建模\rev_1\srl2pal.edf (9365, 2006-01-11)
串并转换建模\rev_1\srl2pal.fse (0, 2006-01-11)
串并转换建模\rev_1\srl2pal.ncf (431, 2006-01-11)
串并转换建模\rev_1\srl2pal.srd (4724, 2006-01-11)
串并转换建模\rev_1\srl2pal.srm (7531, 2006-01-11)
串并转换建模\rev_1\srl2pal.srr (13239, 2006-01-11)
串并转换建模\rev_1\srl2pal.srs (1461, 2006-01-11)
串并转换建模\rev_1\srl2pal.tlg (110, 2006-01-11)
串并转换建模\rev_1\syntmp\srl2pal.msg (0, 2006-01-11)
串并转换建模\rev_1\syntmp\srl2pal.plg (437, 2006-01-11)
串并转换建模\rev_1\verif\srl2pal.vif (1214, 2006-01-11)
串并转换建模\source\srl2pal.v (290, 2006-01-11)
串并转换建模\srl2pal.prd (268, 2006-01-11)
串并转换建模\srl2pal.prj (1397, 2006-01-11)
串并转换建模\srl2pal.v (290, 2006-01-11)
串并转换建模\示例说明.doc (23040, 2006-06-01)
串并转换建模\rev_1\par_1 (0, 2006-06-01)
串并转换建模\rev_1\syntmp (0, 2016-06-12)
串并转换建模\rev_1\verif (0, 2016-06-12)
串并转换建模\rev_1 (0, 2016-06-12)
串并转换建模\source (0, 2016-06-12)
串并转换建模 (0, 2016-06-12)
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