if_single
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：294KB
下载次数：1
上传日期：2016-06-12 15:52:13
上 传 者：
GONGDAYIGE
说明： 所以从语法上讲，多if语句（if... if… if…）可以建模具有优先级的条件判断结构；而单if语句（if...else if…else if…）和case语句可用于建模不带优先级的条件判断。但是随着综合工具优化能力的不断增强，新型的综合工具大多时候会自动优化掉优先级结构，以减少芯片面积，提高时序性能。另外，条件结构的综合结果是否带有优先级不但取决于综合工具的类型和版本，还和目标器件或目标库有直接关系
(Therefore, grammatically, and more if statement (if ... if ... if ...) can be modeled conditional structure having priority while the single if statement (if ... else if ... else if ...) and case statements available in modeling without priority uated. But with the ability to optimize the synthesis tool continuously enhance new integrated tool will automatically optimize away most of the time priority structure to reduce chip area and improve timing performance. In addition, the combined result condition structure with or without priority not only depend on the type and version of the synthesis tools, and also a target device or directly related to the target libraries)
文件列表:
if_single\case\case1.v (392, 2006-01-13)
if_single\case\PrecisionRTL\case.psp (1401, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1.edf (5241, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1.prf (99, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1.xdb (2477, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1_area.rep (1252, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1_con_rep.sdc (312, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1_rtl.ixdb (5382, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1_tech_con_rep.sdc (509, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case1_timing.rep (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\case_impl_1.psi (10786, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\hdlAnalyze_verilogfile (57, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\precision.log (3353, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\precision_rtl.sdc (985, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\precision_tech.sdc (995, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\.rtlc_compile (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\.top (24, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\autotop.conf (65, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\depend\TOPMODULE.list (7, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\emptymod.list (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\hier.list (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\incr_driver.log (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\INCR\incr_rtlc.log (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\legalmodmap.db (38, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\rtlc.args (1862, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\rtlc_args1.file (4095, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc.out\vmw.mem_contents (0, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc_libs\work\case1.mod (3601, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc_libs\work\case1.mod.body (7690, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\rtlc_libs\work\rtlc_version_info (49, 2006-01-16)
if_single\case\PrecisionRTL\case_impl_1\unfolded_operators.txt (0, 2006-01-16)
if_single\case\PrecisionRTL\case_RTL_schematic.bmp (1255542, 2006-01-16)
if_single\case\PrecisionRTL\case_schematic.bmp (899262, 2006-01-16)
if_single\case\PrecisionRTL\Thumbs.db (5632, 2006-05-30)
if_single\case\SynplifyPro\case1.prd (284, 2006-01-13)
if_single\case\SynplifyPro\case1.prj (1172, 2006-01-13)
if_single\case\SynplifyPro\case_rtl_view.bmp (808922, 2006-01-13)
if_single\case\SynplifyPro\case_tech_view.bmp (1180782, 2006-01-13)
if_single\case\SynplifyPro\rev_2\AutoConstraint_case1.sdc (0, 2006-01-13)
if_single\case\SynplifyPro\rev_2\case1.edn (6475, 2006-01-13)
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