sp6ex14
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6081KB
下载次数：14
上传日期：2016-06-20 16:43:21
上 传 者：
pudn_lyg
说明： verilog,ISE工程。倒车雷达实例，每100ms产生1个超声波测距模块所需的10us高脉冲激励，并用数码管以16进制数据显示经过滤波处理的回响信号的高脉冲计数值（以10us为单位），与此同时，蜂鸣器根据障碍物远近，也会相应的发出不同频率的响声。
(verilog, ISE project. Reversing radar instance, every 100ms high pulse generating 10us required an ultrasonic ranging module incentives, and with digital data in hexadecimal display through high pulse count value filter processing echo signals (in 10us units), and this Meanwhile, according to the obstacle distance buzzer will emit different frequencies corresponding sound.)
文件列表:
sp6ex14\counter.lso (6, 2015-07-11)
sp6ex14\counter.prj (38, 2015-07-11)
sp6ex14\counter.stx (1693, 2015-07-11)
sp6ex14\counter.xst (1144, 2015-07-11)
sp6ex14\distance_compute.fdo (1382, 2015-07-11)
sp6ex14\distance_compute.udo (390, 2015-07-11)
sp6ex14\distance_compute_wave.fdo (435, 2015-07-11)
sp6ex14\ipcore_dir\.lso (14, 2015-07-11)
sp6ex14\ipcore_dir\coregen.cgp (237, 2015-07-11)
sp6ex14\ipcore_dir\coregen.log (2510, 2015-07-11)
sp6ex14\ipcore_dir\create_div.tcl (1255, 2015-07-11)
sp6ex14\ipcore_dir\create_mul.tcl (1245, 2015-07-11)
sp6ex14\ipcore_dir\create_pll_controller.tcl (1262, 2015-07-11)
sp6ex14\ipcore_dir\div.asy (632, 2015-07-11)
sp6ex14\ipcore_dir\div.gise (2582, 2015-07-11)
sp6ex14\ipcore_dir\div.ncf (0, 2015-07-11)
sp6ex14\ipcore_dir\div.ngc (251178, 2015-07-11)
sp6ex14\ipcore_dir\div.sym (1828, 2015-07-11)
sp6ex14\ipcore_dir\div.v (347066, 2015-07-11)
sp6ex14\ipcore_dir\div.veo (4790, 2015-07-11)
sp6ex14\ipcore_dir\div.xco (1754, 2015-07-11)
sp6ex14\ipcore_dir\div.xise (4868, 2015-07-11)
sp6ex14\ipcore_dir\div_flist.txt (175, 2015-07-11)
sp6ex14\ipcore_dir\div_xmdf.tcl (2602, 2015-07-11)
sp6ex14\ipcore_dir\edit_pll_controller.tcl (1129, 2015-07-11)
sp6ex14\ipcore_dir\mul\doc\mult_gen_ds255.pdf (302354, 2015-07-11)
sp6ex14\ipcore_dir\mul\doc\mult_gen_v11_2_vinfo.html (7493, 2015-07-11)
sp6ex14\ipcore_dir\mul.asy (421, 2015-07-11)
sp6ex14\ipcore_dir\mul.gise (2582, 2015-07-11)
sp6ex14\ipcore_dir\mul.ncf (0, 2015-07-11)
sp6ex14\ipcore_dir\mul.ngc (24641, 2015-07-11)
sp6ex14\ipcore_dir\mul.sym (1272, 2015-07-11)
sp6ex14\ipcore_dir\mul.v (25497, 2015-07-11)
sp6ex14\ipcore_dir\mul.veo (3756, 2015-07-11)
sp6ex14\ipcore_dir\mul.xco (1903, 2015-07-11)
sp6ex14\ipcore_dir\mul.xise (4868, 2015-07-11)
sp6ex14\ipcore_dir\mul_flist.txt (257, 2015-07-11)
sp6ex14\ipcore_dir\mul_xmdf.tcl (3150, 2015-07-11)
... ...
The following files were generated for 'div' in directory
E:\ds\xilinx_sp6\prj\sp6_ultrasound_seg7mux\ipcore_dir\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* div.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* div.ngc
* div.v
* div.veo
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* div.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* div.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* div.sym
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* div_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* div.gise
* div.xise
Deliver Readme:
Readme file for the IP.
* div_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* div_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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