open_cores_VGAcore
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：2095KB
下载次数：10
上传日期：2011-03-25 08:39:21
上 传 者：
zhangxin0804
说明： 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握
(Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core grasp of bus protocol)
文件列表:
open_cores\vga_core.pdf (405798, 2011-03-05)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\wb_slv_model.v (5299, 2003-05-07)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\wb_model_defines.v (3163, 2003-03-19)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\test_bench_top.v (15511, 2003-09-23)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\tests.v (30463, 2003-09-23)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\sync_check.v (6902, 2003-09-23)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\wb_mast_model.v (6617, 2003-09-23)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\bench\verilog\wb_b3_check.v (6473, 2003-05-07)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\software\include\oc_vga_lcd.h (7298, 2001-11-22)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\sim\rtl_sim\bin\Makefile (4414, 2003-09-23)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\syn\bin\comp.dc (4210, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\syn\bin\design_spec.dc (719, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\syn\bin\read.dc (1877, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\syn\bin\lib_spec.dc (1123, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\doc\vga_core.pdf (405798, 2003-03-20)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_19\doc\src\vga_core_enh.doc (812544, 2003-03-20)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\bench\verilog\wb_slv_model.v (4981, 2002-02-07)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\bench\verilog\wb_model_defines.v (2933, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\bench\verilog\test_bench_top.v (14379, 2002-02-07)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\bench\verilog\tests.v (22562, 2002-04-20)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\bench\verilog\sync_check.v (6263, 2001-11-15)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\bench\verilog\wb_mast_model.v (6396, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\software\include\oc_vga_lcd.h (7298, 2001-11-22)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\sim\rtl_sim\bin\Makefile (3931, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\syn\bin\comp.dc (4210, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\syn\bin\design_spec.dc (719, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\syn\bin\read.dc (1877, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\syn\bin\lib_spec.dc (1123, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\counter.vhd (5748, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\fifo_dc.vhd (4361, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\vtim.vhd (2810, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\vga_and_clut_tstbench.vhd (12910, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\vga_and_clut.vhd (9667, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\fifo.vhd (4108, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\vga.vhd (13257, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\csm_pb.vhd (5870, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\colproc.vhd (8207, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\tgen.vhd (3297, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\wb_master.vhd (14642, 2001-08-21)
open_cores\vga_lcd_latest\vga_lcd\tags\rel_1\rtl\vhdl\dpm.vhd (3215, 2001-08-21)
... ...
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