文件列表:

LvdsSerialAdc (0, 2016-02-23)
LvdsSerialAdc\Documents (0, 2015-04-01)
LvdsSerialAdc\Documents\IMAG0135.jpg (1291364, 2012-05-10)
LvdsSerialAdc\Documents\IMAG0136.jpg (1462429, 2012-05-10)
LvdsSerialAdc\Libraries (0, 2015-12-14)
LvdsSerialAdc\Libraries\Common (0, 2016-02-22)
LvdsSerialAdc\Libraries\Common\Documents (0, 2015-04-01)
LvdsSerialAdc\Libraries\Common\Documents\Visio-AppsRst.pdf (79583, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Documents\Visio-AppsRstEna.pdf (298321, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Documents\Visio-GenPulse.pdf (142849, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Documents\Visio-LifeIndicator.pdf (216902, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Documents\Visio-LocalRstEna.pdf (166955, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Documents\Visio-TimeTickCnt.pdf (155680, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Simscripts (0, 2015-04-01)
LvdsSerialAdc\Libraries\Common\Simscripts\RstEna_FuncComp.prj (4360, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Simscripts\RstEna_FuncFuse.bat (755, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Simscripts\RstEna_FuncSim.bat (671, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Simscripts\RstEna_FuncWave.wcfg (3552, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Simscripts\SimRun.tcl (16, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Simulation (0, 2015-04-01)
LvdsSerialAdc\Libraries\Common\Simulation\DirKeeper.txt (315, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl (0, 2016-02-23)
LvdsSerialAdc\Libraries\Common\Vhdl\AppsRst.vhd (8288, 2013-01-31)
LvdsSerialAdc\Libraries\Common\Vhdl\AppsRstEna.vhd (8276, 2016-02-23)
LvdsSerialAdc\Libraries\Common\Vhdl\AppsRstEna_Testbench.vhd (8676, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\AppsRstEna_Tester.vhd (12813, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\CntFivBit.vhd (9092, 2013-12-02)
LvdsSerialAdc\Libraries\Common\Vhdl\CntFiveBit.vhd (12842, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\CntSixBit.vhd (10679, 2013-12-02)
LvdsSerialAdc\Libraries\Common\Vhdl\CntSixBit_Testbench.vhd (5543, 2011-04-23)
LvdsSerialAdc\Libraries\Common\Vhdl\CntSixBit_Tester.vhd (8390, 2011-04-23)
LvdsSerialAdc\Libraries\Common\Vhdl\Cnt_5b_Bin.vhd (8586, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\Cnt_5b_Gray.vhd (8596, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\Cnt_6b_Bin.vhd (9887, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\Cnt_6b_Gray.vhd (9898, 2014-06-26)
LvdsSerialAdc\Libraries\Common\Vhdl\DeBounce.vhd (10229, 2012-12-07)
LvdsSerialAdc\Libraries\Common\Vhdl\DeBounce_Testbench.vhd (7165, 2012-12-03)
LvdsSerialAdc\Libraries\Common\Vhdl\DeBounce_Tester.vhd (15467, 2012-12-07)
LvdsSerialAdc\Libraries\Common\Vhdl\Fdcr.vhd (7573, 2016-02-23)
... ...

************************************************************************* ____ ____ / /\/ / /___/ \ / \ \ \/ Copyright 2012-2016 Xilinx, Inc. All rights reserved. \ \ This file contains confidential and proprietary / / information of Xilinx, Inc. and is protected under U.S. /___/ /\ and international copyright and other intellectual \ \ / \ property laws. \___\/\___\ ************************************************************************* Vendor: Xilinx readme.txt Version: 1.2 Date Last Modified: 10 Jan 2016 Date Created: 29 Nov 2009 Associated Filename: Xapp524.zip Associated Document: XAPP524, Serial LVDS High-Speed ADC Interface. THIS README FILE IS THE SAME AS THE "Adc_Interface_ReadMe.txt" README FILE! Supported Device: Series-7 ************************************************************************* Disclaimer: This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Critical Applications: Xilinx products are not designed or intended to be fail-safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. ************************************************************************* This document contains the following sections: 1. REVISION HISTORY 2. OVERVIEW 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS 3.1 USED DESIGN ENTRY TOOLS 4. DESIGN FILE HIERARCHY 5. INSTALLATION AND OPERATING INSTRUCTIONS 6. SUPPORT 7. REVISION DETAILS ************************************************************************* 1. REVISION HISTORY Readme Date Version Revision Description ========================================================================= 19/08/2012 1.0 Initial Xilinx release. 23/10/2015 1.1 Updated design files. 10/01/2016 1.2 Port to Vivado + design update. ========================================================================= 1. OVERVIEW: This "readme" describes how to use the contents of the zip file, how and with what tool the designs is made and what to do to obtain extra documentation (pdf) files about the design. 3. SOFTWARE TOOLS AND SYSTEM REQUIREMENTS: Xilinx Vivado_2015.4 or higher. 3.1. USED DESIGN ENTRY TOOLS. Xilinx Vivado_2015.4 or higher. 4. DESIGN FILE HIERARCHY. REMARK: The reference design is only available in VHDL. - The ADC project: LvdsSerialAdc +-- /Documents +-- /Libraries +-- /Common +-- /MmcmClock_Lib +-- /Projects | +-- /Adc_Interface ADC interface project | | +-- /Constraints | | | KC705_AdcToplevel_Toplevel.xdc | | | KC705_Apps_AdcToplevel.xdc | | +-- /Documents Top level project documents. | | +-- /Libraries Libraries used by the top level design. | | | +-- /AdcClock_Lib Each of these directories is used as a library by | | | +-- /AdcData_Lib the top level design. At the same time each of | | | +-- /AdcFrame_Lib these can be used as stand-alone design. The | | | +-- /AdcMem_Lib directory structure is made identical to the | | | +-- /AdcBulkMem_Lib top level directory structure. | | +-- /Simscripts Top level simulation scripts | | +-- /Simulation Top level simulation working directory. | | +-- /Vhdl Top level source code files. | | | Adc_Vhdl_ReadMe.txt Explications about the VHDL source code. | | | AdcIo.vhd | | | AdcToplevel.vhd | | | AdcToplevel_Checker.vhd | | | AdcToplevel_Testbench.vhd | | | AdcToplevel_Tester.vhd | | | AdcToplevel_Toplevel.vhd | | | Adc***45_Tester.vhd | | | Apps_AdcToplevel.vhd | | | AdcInVec.txt Simulation vector file. | | | AdcOutVec.txt Simulations vector file. | | | AdcReadvec.txt Simulation vector file. | | | AdcReadCnst_1_Vec.txt Simulation vector file. | | | AdcReadCnst_2_Vec.txt Simulation vector file. | | +-- /ZipFiles Storage for project related zip files. | | * REMARKS: No remarks. /Libraries Each of the directories in a /Libraries directory is set up as a stand alone project with its own documentation, simulation, and sometimes implementation. The goal is that these smaller designs can be used as standalone design or as component in other designs. The structure of a library is therefore the same as that of a design at a higher hierarchical level. /_Lib +-- /Documents Documents about the library content. +-- /Simscripts Simulation scripts for the library. +-- /Simulation Simulation tool work directory +-- /Vhdl Source code of the library. More later on. Example of a library setup and use: /Libraries /AdcClock_Lib /AdcData_Lib +-- /Documents Documents about the library content. +-- /Simscripts +-- /Simulation +-- /Vhdl | +-- AdcData.vhd | +-- AdcData_Toplevel.vhd /AdcFrame_Lib /AdcMem_Lib /..... / Simulation Storage of the files generated by FUSE. Here simulation .exe file and all log files are stored. /Constraints The /UCF folder from ISE implementation has been converted to a /Constraints folder and contains now XDC files. /Vhdl Here the HDL source code of the design is stored. The directory contains not only the hardware source code but also all the files needed for simulation of the design, except the simulation scripts stored in /SimScripts. The design: AdcToplevel.vhd The files needed for simulation: AdcToplevel_Testbench.vhd Toplevel test bench including all components AdcToplevel_Tester.vhd Sets the input control pins of the ADC AdcToplevel_Checker.vhd Checks the output of the simulation Ads***45_Tester.vhd Mimicking of an ADC Input and output file for/from the simulation: AdcInVec.txt AdcOutVec.txt AdcRead_Vec.txt AdcReadCnst_1_Vec.txt AdcReadCnst_2_Vec.txt Implementation of the top level design with only ADC inputs. AdcToplevel_Toplevel.vhd Implementation of the toplevel design with a small application: AdcIo.vhd Apps_AdcToplevel.vhd 6. TECHNICAL SUPPORT To obtain technical support, create a WebCase at www.xilinx.com/support. uestions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines. 7. REVISION DETAILS. -- 19 Aug 2012 Release of the original design. -- 10 Jan 2016 Design upgraded to Vivado_2015.4

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：