I2C-Master-_-Slave-Core
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：2130KB
下载次数：219
上传日期：2011-03-28 19:28:41
上 传 者：
360073820
说明： 用verilog 实现的 iic 总线编程，包括master，和slave的编程，很详细的iic总线编程
(Iic-bus implemented using verilog programming, including the master, and slave programming, a very detailed iic-bus programming)
文件列表:
i2c_master_slave_core\CVS\Entries (28, 2008-08-28)
i2c_master_slave_core\CVS\Repository (22, 2008-08-28)
i2c_master_slave_core\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\CVS\Entries (52, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\CVS\Repository (44, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\doc\CVS\Entries (106, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\doc\CVS\Repository (48, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\doc\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\doc\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\doc\i2c_spec.doc (571392, 2008-06-26)
i2c_master_slave_core\i2c_master_slave_core\doc\i2c_spec.pdf (835279, 2008-06-26)
i2c_master_slave_core\i2c_master_slave_core\doc (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\CVS\Entries (35, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\CVS\Repository (66, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\CVS\Entries (176, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\CVS\Repository (70, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\i2c_core_verification_plan.pdf (305170, 2008-06-27)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\i2c_spec.doc (571392, 2008-06-27)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc\i2c_spec.pdf (835279, 2008-06-27)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\doc (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\CVS\Entries (58, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\CVS\Repository (71, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\config.sv (808, 2008-06-27)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\CVS\Entries (1175, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\CVS\Repository (80, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\CVS\Root (13, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\CVS (0, 2008-08-28)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\sb_callback.sv (2891, 2008-06-27)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\vmm_clkgen.sv (634, 2008-06-27)
i2c_master_slave_core\i2c_master_slave_core\i2c_master_slave_core\svtb\vmm_svtb\vmm_i2c_callback.sv (473, 2008-06-27)
... ...
This Directory contains all files which are required to run this VMM testbench.
Scripts are not given as it vary from compiler to compiler.
The Basic structure of file system is given below.
vmm_i2c_top.sv
|
|--- vmm_clkgen.sv
|--- vmm_program_test.sv
|
|--- vmm_i2c_env.sv (This is the environment file and all transactors and packet files
are included in this file)
Please note that for transition coverage in register testcase (write-write-read), another file is
availabe which is vmm_program1_test.sv. In this file Scenario_generator_class is extended and
program and top level module is also available.
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