VERILOG-DESIGN
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：31347KB
下载次数：1
上传日期：2016-08-22 10:23:44
上 传 者：
Lnfwnsy
说明： 很多使用Verilog HDL的实例，并有说明，是学习Verilog 不可多得的好资料。
(many Verilog HDL examples and has made it clear that it is rare to learn Verilog good information.)
文件列表:
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.(0).cnf.cdb (1862, 2011-03-11)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.(0).cnf.hdb (1195, 2011-03-11)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.amm.cdb (220, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.asm.qmsg (2204, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.asm.rdb (1350, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.asm_labs.ddb (11286, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cbx.xml (91, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp.bpm (698, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp.cdb (6744, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp.hdb (10272, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp.kpt (200, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp.logdb (12929, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp.rdb (17684, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cmp_merge.kpt (204, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd (396304, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cuda_io_sim_cache.31um_ss_1200mv_85c_slow.hsd (387195, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd (346788, 2011-02-24)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd (394406, 2011-02-24)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.db_info (138, 2010-12-22)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.fit.qmsg (16284, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.hier_info (586, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.hif (762, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.idb.cdb (1623, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.lpc.html (430, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.lpc.rdb (388, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.lpc.txt (1060, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map.bpm (675, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map.cdb (2446, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map.hdb (9682, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map.kpt (202, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map.logdb (4, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map.qmsg (4908, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map_bb.cdb (1105, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map_bb.hdb (8574, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.map_bb.logdb (4, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.pre_map.cdb (2199, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.pre_map.hdb (9517, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.rtlv.hdb (9496, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.rtlv_sg.cdb (1791, 2011-05-04)
VERILOG设计实例\10__encode8_3_BCD\db\encode8_3.rtlv_sg_swap.cdb (177, 2011-05-04)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
近期下载者：
相关文件：
收藏者：