FSK
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：109KB
下载次数：29
上传日期：2011-03-31 14:28:29
上 传 者：
liyuhuan1694
说明： 利用FPGA内的IP核来实现FSK，Using FPGA to realize the IP core FSK。
(Using FPGA to realize the IP core FSK,)
文件列表:
FSK\use10.v (1763, 2009-10-14)
FSK\DS16101.v (3211, 2009-10-15)
FSK\fsk.v (8323, 2009-10-19)
FSK\my_cic.bsf (3371, 2009-09-22)
FSK\my_cic4.bsf (3372, 2007-03-31)
FSK\my_cic4.v (7827, 2007-03-31)
FSK\my_cic4_bb.v (2045, 2007-03-31)
FSK\my_cic4_cic.vhd (15288, 2007-03-31)
FSK\my_cic4_fir_comp_coeff.m (8361, 2007-03-31)
FSK\my_cic4_tb.v (5551, 2007-03-31)
FSK\my_cic7.bsf (3372, 2009-09-24)
FSK\my_cic7.v (7827, 2009-09-24)
FSK\my_cic7_bb.v (2045, 2009-09-24)
FSK\my_cic7_cic.vhd (17824, 2009-09-24)
FSK\my_cic7_fir_comp_coeff.m (8360, 2009-09-24)
FSK\my_cic7_tb.v (5552, 2009-09-24)
FSK\my_cic_bb.v (2044, 2009-09-22)
FSK\my_cic_cic.vhd (14440, 2009-09-22)
FSK\my_cic_fir_comp_coeff.m (8355, 2009-09-22)
FSK\my_cic_tb.v (5543, 2009-09-22)
FSK\my_fir.bsf (3292, 2011-03-31)
FSK\my_fir.v (10852, 2011-03-31)
FSK\my_fir_ast.vhd (6484, 2011-03-31)
FSK\my_fir_bb.v (2131, 2011-03-31)
FSK\my_fir_mlab.m (7028, 2011-03-31)
FSK\my_fir_model.m (4618, 2011-03-31)
FSK\my_fir_st.v (26738, 2011-03-31)
FSK\my_mul.bsf (2456, 2011-03-31)
FSK\my_mul.v (4814, 2011-03-31)
FSK\my_mul_bb.v (4168, 2011-03-31)
FSK\my_mul_inst.v (124, 2011-03-31)
FSK\my_nco.bsf (2377, 2011-03-31)
FSK\my_nco.v (10638, 2011-03-31)
FSK\my_nco_bb.v (1873, 2011-03-31)
FSK\my_nco_model.m (1342, 2011-03-31)
FSK\my_nco_st.v (18480, 2011-03-31)
FSK\my_nco_tb.m (1617, 2011-03-31)
FSK\my_nco_tb.v (2374, 2011-03-31)
FSK\my_nco_tb.vhd (4022, 2011-03-31)
FSK\my_ram.bsf (5313, 2009-10-13)
... ...
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