14_ethernet_test
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7208KB
下载次数：70
上传日期：2016-10-28 10:02:45
上 传 者：
accountm
说明： 这是利用FPGA实现对以太网传输的控制。FPGA为Spartan 6 LX16，以太网芯片为RTL8211。千兆传输速率。语言为Verilog，但没找到这一选项，故选择了最接近的VHDL
(This is achieved using the FPGA Ethernet transmission control. FPGA for the Spartan 6 LX16, Ethernet chip RTL8211. Gigabit transmission rate.)
文件列表:
14_ethernet_test\11.wcfg (2938, 2015-11-04)
14_ethernet_test\chipscope.cdc (7134, 2015-11-04)
14_ethernet_test\chipscope_icon.asy (193, 2015-11-04)
14_ethernet_test\chipscope_icon.constraints\chipscope_icon.ucf (375, 2015-11-04)
14_ethernet_test\chipscope_icon.constraints\chipscope_icon.xdc (793, 2015-11-04)
14_ethernet_test\chipscope_icon.gise (1282, 2015-11-04)
14_ethernet_test\chipscope_icon.ncf (375, 2015-11-04)
14_ethernet_test\chipscope_icon.ngc (31988, 2015-11-04)
14_ethernet_test\chipscope_icon.ucf (375, 2015-11-04)
14_ethernet_test\chipscope_icon.v (892, 2015-11-04)
14_ethernet_test\chipscope_icon.veo (1083, 2015-11-04)
14_ethernet_test\chipscope_icon.xco (1667, 2015-11-04)
14_ethernet_test\chipscope_icon.xdc (793, 2015-11-04)
14_ethernet_test\chipscope_icon_flist.txt (421, 2015-11-04)
14_ethernet_test\chipscope_icon_xmdf.tcl (3321, 2015-11-04)
14_ethernet_test\chipscope_ila.asy (353, 2015-11-04)
14_ethernet_test\chipscope_ila.cdc (14677, 2015-11-04)
14_ethernet_test\chipscope_ila.constraints\chipscope_ila.ucf (440, 2015-11-04)
14_ethernet_test\chipscope_ila.constraints\chipscope_ila.xdc (477, 2015-11-04)
14_ethernet_test\chipscope_ila.gise (1279, 2015-11-04)
14_ethernet_test\chipscope_ila.ncf (384, 2015-11-04)
14_ethernet_test\chipscope_ila.ngc (919696, 2015-11-04)
14_ethernet_test\chipscope_ila.ucf (440, 2015-11-04)
14_ethernet_test\chipscope_ila.v (946, 2015-11-04)
14_ethernet_test\chipscope_ila.veo (1139, 2015-11-04)
14_ethernet_test\chipscope_ila.xco (4393, 2015-11-04)
14_ethernet_test\chipscope_ila.xdc (477, 2015-11-04)
14_ethernet_test\chipscope_ila_flist.txt (442, 2015-11-04)
14_ethernet_test\chipscope_ila_xmdf.tcl (3301, 2015-11-04)
14_ethernet_test\clock.cdc (731, 2016-08-19)
14_ethernet_test\coregen.cgc (63878, 2015-11-04)
14_ethernet_test\coregen.cgp (522, 2015-11-04)
14_ethernet_test\ethernet.bgn (8863, 2015-11-04)
14_ethernet_test\ethernet.bld (4055, 2015-11-04)
14_ethernet_test\ethernet.cfi (431, 2015-11-04)
14_ethernet_test\ethernet.cmd_log (123080, 2015-11-04)
14_ethernet_test\ethernet.drc (2630, 2015-11-04)
14_ethernet_test\ethernet.lso (6, 2015-11-04)
... ...
The following files were generated for 'chipscope_ila' in directory
E:\Project\AX516\verilog\ethernet_test\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* chipscope_ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* chipscope_ila.cdc
* chipscope_ila.constraints/chipscope_ila.ucf
* chipscope_ila.constraints/chipscope_ila.xdc
* chipscope_ila.ncf
* chipscope_ila.ngc
* chipscope_ila.ucf
* chipscope_ila.v
* chipscope_ila.veo
* chipscope_ila.xdc
* chipscope_ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* chipscope_ila.asy
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* chipscope_ila.gise
* chipscope_ila.xise
Deliver Readme:
Readme file for the IP.
* chipscope_ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* chipscope_ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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