UART11

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:49KB
下载次数:6
上传日期:2011-04-03 20:46:25
上 传 者莫名儿
说明:  uart实现,原理图方式,介绍串口实现的模块及实现方式
(uart implementation schematic way to introduce the serial interface modules and implementations)

文件列表:
UART11\uart_v11\clk_pdiv.acf (14721, 2004-11-07)
UART11\uart_v11\clk_pdiv.hif (1522, 2004-11-07)
UART11\uart_v11\clk_pdiv.inc (1591, 1998-04-05)
UART11\uart_v11\clk_pdiv.sym (477, 1998-04-05)
UART11\uart_v11\clk_pdiv.tdf (3558, 1998-04-16)
UART11\uart_v11\filterx.inc (1625, 1998-04-16)
UART11\uart_v11\filterx.sym (513, 1998-04-16)
UART11\uart_v11\filterx.tdf (3289, 1998-04-16)
UART11\uart_v11\filt_tpl.inc (1562, 1998-04-16)
UART11\uart_v11\filt_tpl.sym (308, 1998-04-16)
UART11\uart_v11\filt_tpl.tdf (3342, 1998-04-16)
UART11\uart_v11\Par_Gen.inc (1554, 1998-03-24)
UART11\uart_v11\Par_Gen.sym (293, 1998-03-24)
UART11\uart_v11\Par_Gen.tdf (3114, 1998-04-16)
UART11\uart_v11\rx.sym (962, 1998-08-06)
UART11\uart_v11\rx.tdf (13185, 1998-08-07)
UART11\uart_v11\shiftreg.inc (1640, 1998-04-02)
UART11\uart_v11\shiftreg.sym (615, 1998-04-02)
UART11\uart_v11\shiftreg.tdf (4726, 1998-04-16)
UART11\uart_v11\tx.sym (848, 1998-08-03)
UART11\uart_v11\tx.tdf (11572, 1998-08-07)
UART11\uart_v11\uart.acf (14721, 2004-11-07)
UART11\uart_v11\uart.gdf (8376, 1998-08-06)
UART11\uart_v11\uart.hif (1612, 2006-09-11)
UART11\uart_v11\uart.inc (1640, 1998-08-03)
UART11\uart_v11\uart.sym (1052, 1998-08-07)
UART11\uart_v11\uartctrl.sym (1846, 1998-08-06)
UART11\uart_v11\uartctrl.tdf (39283, 1998-08-07)
UART11\uart_v11\uarttest.acf (19437, 2006-09-11)
UART11\uart_v11\uarttest.gdf (3714, 1998-08-07)
UART11\uart_v11\uarttest.hif (1662, 2006-09-11)
UART11\uart_v11\uarttest.scf (34997, 1998-08-07)
UART11\uart_v11 (0, 2010-04-30)
UART11 (0, 2010-04-30)

PROJECT: Programmable Universal Asynchronous Receiver/Transmitter. Version 1.1 Keith Willis Copyright 19***. All Rights Reserved. You may use or distribute these files freely, provided you do not remove this copyright notice or modify the contents of the files. If you have questions or comments, feel free to contact me by email at kcwillis@mech.eng.usyd.edu.au --------------------------------------------------------------------------------------- The UART.ZIP file contains all of the necessary Max+plusII V8.2 design files for a fully-programmable UART. If you have Max+PlusII V8.2 then simply load the project file UARTTEST.GDF. There is a full simulation in the file UARTTEST.SCF. All the necessary ancillary files have been included in this collection. These include some useful files in their own right such as the following: A Parametized Parity Generator, (Width). A Parametized Digital Filter, (Depth and Width). A Parametized/Programmable Clock Divider, (Width) optimized for area and speed. --------------------------------------------------------------------------------------- UART MANUAL: --------------------------------------------------------------------------------------- ADDRESS MAP: =========================================== | ADDRESS | REGISTER | =========================================== | $00 (READ) | RECEIVED DATA REGISTER | ------------------------------------------- | $00 (WRITE)| TRANSMITTED DATA REGISTER | =========================================== | $01 (READ) | STATUS REGISTER | ------------------------------------------- | $01 (WRITE)| CONFIGURATION REGISTER | =========================================== | $02 (WRITE)| BAUD-RATE REGISTER | =========================================== | $03 (R/W) | HANDSHAKING REGISTER | =========================================== --------------------------------------------------------------------------------------- CPU INTERFACE: Di[7..0]: Input Data Bus. This bus may be used when embedding the UART module into a larger EPLD design. Do[7..0]: Multiplexed Output Data Bus. This bus may be used when embedding the UART module into a larger EPLD design. D7-D0: 8-bit Bidirectional Data Bus. This bus may also be used as the input data bus when embedding the UART module into a larger EPLD design. A1-A0: 2-bit Address Bus, decodes the internal UART registers. CS: Active-High Chip Select. RD: Active-High Read. WR: Active-High Write. RESET: Active-High Reset. CLK: Master clock for UART, default=40MHz. INT: Active High Interrupt = SENT OR RCVD. SENT: Active-High Receiver Interrupt. RCVD: Active-High Tranmitter Interrupt. --------------------------------------------------------------------------------------- REGISTER BIT FIELDS: ================= | STATUS REGISTER | ================================================================================================ | 0 | 0 | OV | FE | PE | SE | DR | DT | ================================================================================================ DT: DATA TRANSMITTED FLAG DR: DATA RECEIVED FLAG SE: START BIT ERROR FLAG PE: PARITY ERROR FLAG FE: FRAMING ERROR FLAG OV: OVERUN ERROR FLAG DATA TRANSMITTED FLAG: The data transmitted flag is set to 1 at the completion of a byte transmission. It is automatically cleared to 0 when a new byte is written to the data transmit register. DATA RECEIVED FLAG: The data received flag is set to 1 at the successful completion of a byte receive cycle. It is automatically cleared to 0 when the Rx Data Register is read. If a new byte is received before an Rx Data Register read, the over run flag will be set to 1. If the (SR) status option is set the UART will ignore all further incoming bytes until the Rx Data Register has been read. START BIT ERROR FLAG: The start bit error flag is set to 1 if an invalid start bit is encountered. It is automatically cleared to 0 when the Rx Data Register is read. PARITY ERROR FLAG: The parity error flag is set to 1 if an invalid parity bit is encountered. It is automatically cleared to 0 when the Rx Data Register is read. FRAMING ERROR FLAG: The framing error flag is set to 1 if an invalid stop bit is encountered. It is automatically cleared to 0 when the Rx Data Register is read. OVERRUN ERROR FLAG: The overrun error flag is set to 1 if a new byte is received before the UART Rx Data Register has been read to clear the Rx Status flags from the previous receive cycle. ========================== | CONFIGURATION REGISTER 0 | =============================================================================================== | Reserved | HS | D1 | D0 | S1 | S0 | P1 | P0 | =============================================================================================== P1-P0: PARITY TYPE 00 = NO PARITY (DEFAULT) 01 = ODD PARITY 10 = EVEN PARITY 11 = NO PARITY S1-S0: NUMBER OF STOP BITS 00 = 1 STOP BIT (DEFAULT) 01 = 1.5 STOP BITS 10 = 2 STOP BITS 11 = 1 STOP BIT D1-D0: NUMBER OF DATA BITS 00 = 5 DATA BITS 01 = 6 DATA BITS 10 = 7 DATA BITS 11 = 8 DATA BITS HS: HANDSHAKING OPTION 0 = NO HANDSHAKING (CONTROLLED EXTERNALLY) 1 = LOCAL HANDSHAKING HANDSHAKING OPTION: Handshaking using the /RTS, /CTS, /DTR, /DSR signals may be performed locally by the UART if the handshaking option bit is set to 1. When the receiver is ready to receive a byte /RTS and /DTR are held low. After the first byte has been received, /RTS and /DTR remain low unless a new start bit is detected, before the existing byte held in the Rx Data Register has been read. If this is the case then /RTS and /DTR will be set high, and the receiver will continue to receive the new incoming byte. If the Rx Data Register has not been read when the new byte has been received, then the Data Overrun flag will be set, the Rx Data will be transferred to the Rx Data Register, and the Rx Data Received Flag will be set. If the handshaking option bit is set to 0, these signals become general-purpose I/O with /RTS and /DTR as outputs and /CTS and /DSR as inputs. It then becomes the responsibility of the host CPU to manage these signals. ==================== | BAUD-RATE REGISTER | =============================================================================================== | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | =============================================================================================== B7-B0: BAUD RATE SELECTION 0000 = 1200 0001 = 2400 0010 = 4800 0011 = 9600 0100 = 14400 0101 = 19200 0110 = 28800 0111 = 38400 1000 = 57600 1001 = 115200 >1001 = FCLK/(2*B[6..0] + 2) USER-DEFINED BAUD RATE SELECTION: If a byte greater than H:09 is written to the baud rate selection register, this is used to directly calculate a user- defined baud rate according to the following formula: Fbaud = FCLK / (2 * B[6..0] + 2) (Special Case) H:80 is invalid and will lock out the UART. ====================== | HANDSHAKING REGISTER | =============================================================================================== (R)| 0 | 0 | 0 | 0 | 0 | 0 | DSR | CTS | ----------------------------------------------------------------------------------------------- (W)| Reserved | Reserved | Reserved | Reserved | Reserved | Reserved | DTR | RTS | =============================================================================================== --------------------------------------------------------------------------------------- FEATURES: - Master clock frequency(FCLK) is entered as a module parameter. - Maximum master clock frequency=50MHz for -2 grade parts. - Maximum Bit Rate=12.5MBits/s at FCLK=50MHz for -2 grade parts. ... ...

近期下载者

相关文件


收藏者