dvi_demo
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：46KB
下载次数：34
上传日期：2016-11-04 15:23:08
上 传 者：
swimmer
说明： verilog实现的DVI 视频编码输出与输入，已在altera Cyclone IV 上实现。
(DVI encode and decode in Verlog language.Have been tested in altera FPGA Cycloene IV )
文件列表:
dvi_demo\rtl\common\debnce.v (3700, 2008-07-24)
dvi_demo\rtl\common\DRAM16XN.v (1667, 2008-07-24)
dvi_demo\rtl\common\hdclrbar.v (17508, 2008-07-24)
dvi_demo\rtl\common\synchro.v (3890, 2008-07-24)
dvi_demo\rtl\common\timing.v (8425, 2008-07-24)
dvi_demo\rtl\dvitx_demo.v (22213, 2008-09-19)
dvi_demo\rtl\dvi_demo.v (13116, 2008-07-24)
dvi_demo\rtl\logofly\autopilot.v (10272, 2008-07-24)
dvi_demo\rtl\logofly\cursor_pair.v (5809, 2008-07-24)
dvi_demo\rtl\logofly\s3a_logo.v (36831, 2008-07-24)
dvi_demo\rtl\rx\chnlbond.v (5887, 2008-07-24)
dvi_demo\rtl\rx\dcminit.v (4701, 2008-07-24)
dvi_demo\rtl\rx\decode.v (10479, 2008-07-24)
dvi_demo\rtl\rx\dvi_decoder.v (6242, 2008-07-24)
dvi_demo\rtl\rx\phsaligner.v (18475, 2008-07-24)
dvi_demo\rtl\rx\tmds_1c_1to10.v (8751, 2008-07-24)
dvi_demo\rtl\tx\dvi_encoder.v (3959, 2008-07-24)
dvi_demo\rtl\tx\encode.v (7601, 2008-07-24)
dvi_demo\rtl\tx\serdes_4b_10to1_fifo.v (14335, 2008-07-24)
dvi_demo\rtl\common (0, 2014-05-17)
dvi_demo\rtl\logofly (0, 2014-05-17)
dvi_demo\rtl\rx (0, 2014-05-17)
dvi_demo\rtl\tx (0, 2014-05-17)
dvi_demo\rtl (0, 2014-05-17)
dvi_demo (0, 2014-05-17)
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