Asynchronous-FIFO-design

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:3KB
下载次数:20
上传日期:2011-04-07 18:28:24
上 传 者wzl900813
说明:  异步FIFO是一种先进先出的电路,在异步电路中,由于时钟之间周期和相位完全独立,因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点,本代码介绍了一种解决方法。
(Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss probability is not zero. How to design a high reliability, high speed asynchronous FIFO is a difficulty, this code introduced a kind of solution. )

文件列表:
异步FIFO设计\async_cmp.v (703, 2006-12-05)
异步FIFO设计\async_fifo.v (1420, 2006-12-05)
异步FIFO设计\dp_ram.v (516, 2006-12-05)
异步FIFO设计\rptr_empty.v (799, 2006-12-05)
异步FIFO设计\wptr_full.v (832, 2006-12-05)
异步FIFO设计 (0, 2011-04-06)

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