Detection0X47
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:5525KB
下载次数:5
上传日期:2017-01-06 20:15:15
上 传 者:
凡茜
说明: verilog DVB 扰码设计 0x47
(verilog DVB- scrambling design)
文件列表:
Detection0X47\addr.cmd_log (203, 2016-06-21)
Detection0X47\addr.tfi (118, 2016-06-21)
Detection0X47\addr.v (732, 2016-06-21)
Detection0X47\addr_test.v (1007, 2016-06-21)
Detection0X47\addr_test_isim_beh.exe (94720, 2016-06-22)
Detection0X47\addr_test_isim_beh.wdb (13055, 2016-06-22)
Detection0X47\addr_test_isim_beh1.wdb (768871, 2016-06-21)
Detection0X47\addr_test_stx_beh.prj (137, 2016-06-22)
Detection0X47\data_save.v (1627, 2016-06-21)
Detection0X47\Detection0X47.cmd_log (244, 2016-06-18)
Detection0X47\Detection0X47.gise (22448, 2016-06-28)
Detection0X47\Detection0X47.lso (6, 2016-06-21)
Detection0X47\Detection0X47.ngc (4195, 2016-06-18)
Detection0X47\Detection0X47.ngr (1651, 2016-06-18)
Detection0X47\Detection0X47.prj (32, 2016-06-21)
Detection0X47\Detection0X47.stx (1759, 2016-06-21)
Detection0X47\Detection0X47.syr (15190, 2016-06-18)
Detection0X47\Detection0X47.v (2032, 2016-06-21)
Detection0X47\Detection0X47.xise (41349, 2016-06-28)
Detection0X47\Detection0X47.xst (1173, 2016-06-21)
Detection0X47\Detection0X47_envsettings.html (9479, 2016-06-21)
Detection0X47\Detection0X47_summary.html (5403, 2016-06-21)
Detection0X47\Detection0X47_test_tb.v (5772, 2016-06-28)
Detection0X47\Detection0X47_test_tb_isim_beh.exe (94720, 2016-06-16)
Detection0X47\Detection0X47_test_tb_isim_beh1.wdb (124167, 2016-06-16)
Detection0X47\Detection0X47_test_tb_stx_beh.prj (158, 2016-06-16)
Detection0X47\Detection0X47_xst.xrpt (11965, 2016-06-18)
Detection0X47\DetectionSYN.lso (6, 2016-06-18)
Detection0X47\DetectionSYN.prj (31, 2016-06-18)
Detection0X47\DetectionSYN.stx (1689, 2016-06-18)
Detection0X47\DetectionSYN.v (1930, 2016-06-20)
Detection0X47\DetectionSYN.xst (1125, 2016-06-18)
Detection0X47\DetectionSYN_isim_beh.exe (94720, 2016-06-20)
Detection0X47\DetectionSYN_test_tb.v (6318, 2016-06-16)
Detection0X47\DetectionSYN_test_tb_isim_beh.exe (94720, 2016-06-20)
Detection0X47\DetectionSYN_test_tb_isim_beh1.wdb (4585555, 2016-06-16)
Detection0X47\DetectionSYN_test_tb_stx_beh.prj (156, 2016-06-20)
Detection0X47\dvb.cdc (1677, 2016-06-21)
Detection0X47\fuse.log (1182, 2016-06-22)
Detection0X47\fuse.xmsgs (367, 2016-06-22)
... ...
The following files were generated for 'icon_pro' in directory
C:\Users\Administrator\Desktop\EDA\Detection0X47\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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