ddsfinal1
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1111KB
下载次数：214
上传日期：2011-04-08 20:14:14
上 传 者：
zifeng516
说明： verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真
(verilog language dds code,modelsim debug)
文件列表:
ddsfinal1\rom_syn.v (6756, 2010-08-25)
ddsfinal1\dds_final.v (867, 2010-08-29)
ddsfinal1\nmux4.v (261, 2010-08-25)
ddsfinal1\decoder_38.v (347, 2009-12-19)
ddsfinal1\dds.v (3045, 2010-08-25)
ddsfinal1\rom.mif (6542, 2010-08-24)
ddsfinal1\dds_final.qpf (1281, 2010-08-25)
ddsfinal1\dds_final.qsf (5911, 2010-12-15)
ddsfinal1\dds_final.map.summary (473, 2010-12-15)
ddsfinal1\dds_final.pin (20332, 2010-12-15)
ddsfinal1\dds_final.fit.smsg (513, 2010-12-15)
ddsfinal1\dds_final.fit.summary (609, 2010-12-15)
ddsfinal1\dds_final.sof (151064, 2010-12-15)
ddsfinal1\dds_final.pof (524488, 2010-12-15)
ddsfinal1\dds_final.tan.summary (1881, 2010-12-15)
ddsfinal1\dds_final.v.bak (870, 2010-08-29)
ddsfinal1\dds_final.merge.rpt (12061, 2010-09-07)
ddsfinal1\dds_final.done (26, 2010-12-15)
ddsfinal1\dds_final_nativelink_simulation.rpt (1024, 2010-12-15)
ddsfinal1\rom_syn_waveforms.html (1648, 2010-08-25)
ddsfinal1\rom_syn_wave0.jpg (106648, 2010-08-25)
ddsfinal1\rom_syn_wave1.jpg (126431, 2010-08-25)
ddsfinal1\rom_syn.inc (882, 2010-08-25)
ddsfinal1\rom_syn.bsf (3439, 2010-08-25)
ddsfinal1\rom_syn_inst.v (118, 2010-08-25)
ddsfinal1\rom_syn_bb.v (5352, 2010-08-25)
ddsfinal1\rom_syn.qip (542, 2010-08-25)
ddsfinal1\dds.bsf (2557, 2010-08-25)
ddsfinal1\dds_final.bsf (2979, 2010-08-25)
ddsfinal1\decoder_38.bsf (1617, 2010-08-25)
ddsfinal1\nmux4.bsf (2537, 2010-08-25)
ddsfinal1\dds_final.dpf (239, 2010-08-30)
ddsfinal1\dds_final.cdf (326, 2010-08-29)
ddsfinal1\simulation\modelsim\dds_final_modelsim.xrf (38795, 2010-12-15)
ddsfinal1\simulation\modelsim\dds_final.vo (305320, 2010-12-15)
ddsfinal1\simulation\modelsim\dds_final_v.sdo (294539, 2010-12-15)
ddsfinal1\simulation\modelsim\dds_final_run_msim_rtl_verilog.do.bak2 (814, 2010-08-29)
ddsfinal1\simulation\modelsim\dds_final_run_msim_rtl_verilog.do (814, 2010-12-15)
ddsfinal1\simulation\modelsim\dds_final_run_msim_rtl_verilog.do.bak3 (814, 2010-08-30)
ddsfinal1\simulation\modelsim\dds_final_run_msim_rtl_verilog.do.bak4 (814, 2010-08-30)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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