is95receiver
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：112KB
下载次数：39
上传日期：2011-04-11 12:09:50
上 传 者：
zin2010
说明： CDMA IS-95 接收机基带处理仿真 对扩频原理学习有所帮助
(CDMA IS-95 receiver )
文件列表:
终端基带处理\agc.vhd (2038, 2008-10-06)
终端基带处理\check_fault_lock.vhd (7823, 2008-11-07)
终端基带处理\clk_gen.vhd (3395, 2008-10-07)
终端基带处理\clk_gen_b.vhd (5076, 2008-10-10)
终端基带处理\convert.vhd (1086, 2009-01-15)
终端基带处理\convert.vhd.bak (1086, 2009-01-15)
终端基带处理\convert_pag.vhd (1092, 2008-12-10)
终端基带处理\convert_traf.vhd (1095, 2008-12-10)
终端基带处理\corelate.vhd (6207, 2008-10-07)
终端基带处理\corelate_0.vhd (7137, 2008-10-03)
终端基带处理\correlative_add.vhd (9649, 2008-10-03)
终端基带处理\cos_tab.hex (746, 2000-02-13)
终端基带处理\data_extract.vhd (1577, 2008-10-13)
终端基带处理\deexpand.vhd (4290, 2008-12-10)
终端基带处理\deexpand_1.vhd (6273, 2008-10-12)
终端基带处理\deintertraf.vhd (4008, 2008-10-13)
终端基带处理\delay_1.vhd (549, 2008-06-02)
终端基带处理\delay_10.vhd (746, 2008-06-02)
终端基带处理\delay_125.vhd (755, 2008-12-10)
终端基带处理\delay_13.vhd (749, 2008-08-03)
终端基带处理\delay_14.vhd (749, 2008-09-06)
终端基带处理\delay_15.vhd (749, 2008-09-07)
终端基带处理\delay_16.vhd (749, 2008-09-08)
终端基带处理\delay_165.vhd (755, 2008-10-09)
终端基带处理\delay_17.vhd (750, 2008-06-05)
终端基带处理\delay_177.vhd (755, 2008-10-13)
终端基带处理\delay_18.vhd (749, 2008-09-14)
终端基带处理\delay_19.vhd (749, 2008-08-03)
终端基带处理\delay_2.vhd (611, 2008-10-15)
终端基带处理\delay_20.vhd (749, 2008-08-03)
终端基带处理\delay_21.vhd (749, 2008-06-02)
终端基带处理\delay_22.vhd (749, 2008-06-02)
终端基带处理\delay_23.vhd (749, 2008-09-08)
终端基带处理\delay_25.vhd (749, 2008-06-02)
终端基带处理\delay_3.vhd (670, 2008-09-09)
终端基带处理\delay_4.vhd (743, 2008-09-08)
终端基带处理\delay_5.vhd (743, 2008-06-02)
终端基带处理\delay_5up.vhd (749, 2008-09-10)
终端基带处理\delay_6.vhd (743, 2008-10-13)
终端基带处理\delay_7.vhd (743, 2008-09-16)
... ...
## BianXieZhan( 76.8k x 2 )主后处理程序组成及说明：##
* brkn_vt90.vhd -- 主程序顶层文件
* postbr_90.vhd -- 后处理核心模块
* clk_genb.vhd -- 时钟产生模块
* pnw_genb.vhd -- PN码产生模块
* corelate40.vhd -- 相关累加模块
* ph_loop.vhd -- 锁相环处理模块
pipe_mult.vhd -- 流水线乘法器
demux1.vhd -- 话音解复接模块
squaren_add.vhd -- 平方和模块
square_n.vhd -- 平方模块
asyn_rom_256x8.vhd -- 异步ROM，乘法查找表
udiv_16d8.vhd -- 无符号除法器模块，16位除以8位
check7eh.vhd -- 7EH的帧头检查程序，如一段时间没有7EH，则判断为假锁并自动进入重新同步
postpack.vhd -- 公用程序包
（注：Viterbi译码模块在发片FPGA中）
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