S27_SDRAM_IP
所属分类：驱动编程
开发工具：Others
文件大小：6687KB
下载次数：3
上传日期：2017-02-23 20:44:02
上 传 者：
星辰夜
说明： SDRAM 驱动读写demo，用verilog写的上板测试过
(SDRAM verilog)
文件列表:
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\Command.v (17967, 2010-06-03)
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\control_interface.v (8494, 2010-06-07)
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\Params.v (935, 2010-06-07)
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\sdram.v (6881, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\sdram_driver.v (4203, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\sdr_data_path.v (2760, 2010-06-03)
S27_SDRAM_IP\sdram_4m16_LX45_80M\rtl\sdr_sdram.v (7015, 2010-06-07)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\Command.v (17967, 2010-06-03)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\control_interface.v (8494, 2010-06-07)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\coregen.cgc (66280, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\coregen.cgp (530, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\coregen.log (111, 2016-03-31)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\coregen.rsp (169, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\create_sdram.tcl (1270, 2016-03-31)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.asy (189, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.gise (1369, 2011-05-10)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.ncf (0, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.ngc (31200, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.v (39847, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.veo (1080, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.vhd (44284, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.vho (1315, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.xco (1376, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram.xise (5029, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram_flist.txt (275, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\icon_sdram_xmdf.tcl (2882, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.asy (348, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.cdc (2598, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.gise (2603, 2011-05-10)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.ncf (0, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.ngc (246446, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.v (430649, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.veo (1135, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.vhd (467567, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.vho (1419, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.xco (4043, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram.xise (5022, 2011-05-09)
S27_SDRAM_IP\sdram_4m16_LX45_80M\sdram_LX45\ipcore_dir\ila_sdram_flist.txt (277, 2011-05-09)
... ...
The following files were generated for 'ila_sdram' in directory
D:\V3FPGA\LX45_BOARD\memory\sdram_LX45\sdram_LX45\ipcore_dir\
ila_sdram.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
ila_sdram.cdc:
Please see the core data sheet.
ila_sdram.gise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ila_sdram.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
ila_sdram.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
ila_sdram.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
ila_sdram.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
ila_sdram.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
ila_sdram.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
ila_sdram.xise:
ISE Project Navigator support file. This is a generated file and should
not be edited directly.
ila_sdram_readme.txt:
Text file indicating the files generated and how they are used.
ila_sdram_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
ila_sdram_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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