cpld_spi
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1031KB
下载次数：135
上传日期：2011-04-13 09:45:56
上 传 者：
liliugang
说明： cpld spi ，功能基本上满足普通项目的使用，欢迎使用。
(cpld spi, function essentially to meet the general project use, Welcome.)
文件列表:
CPLD_SPI (0, 2001-01-01)
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e.rar (110978, 2009-04-26)
CPLD_SPI\an485_CN.pdf (228304, 2009-04-26)
CPLD_SPI\an485_design_example.zip (312268, 2009-04-26)
CPLD_SPI\detail384641.htm (16951, 2009-04-26)
CPLD_SPI\基于CPLD的SPI总线试验简单程序 - forever的日志 - 网易博客.mht (1146349, 2009-04-26)
CPLD_SPI\基于CPLD的SPI总线试验简单程序【转】 - wenstar的个人空间 - 电子工程世界 - Powered by X-Space.mht (176941, 2009-04-26)
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e (0, 2001-01-01)
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e\ModelSim_ tb_spi().pdf (231459, 2008-08-31)
CPLD_SPI\6a26531a-afd2-4517-a09b-1780b91fc30e\spi.v (4190, 2008-08-31)
CPLD_SPI\an485_design_example (0, 2001-01-01)
CPLD_SPI\an485_design_example\code (0, 2001-01-01)
CPLD_SPI\an485_design_example\code\SPI_Master.v (5023, 2007-02-08)
CPLD_SPI\an485_design_example\modelsim (0, 2001-01-01)
CPLD_SPI\an485_design_example\modelsim\SPI_Master.cr.mti (1105, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\SPI_Master.mpf (10100, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\SPI_Master.v (5023, 2007-02-08)
CPLD_SPI\an485_design_example\modelsim\SPI_Master_test.v (10393, 2007-02-10)
CPLD_SPI\an485_design_example\modelsim\SPI_Master_test.v.bak (10393, 2007-02-08)
CPLD_SPI\an485_design_example\modelsim\transcript (2236, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\vsim.wlf (40960, 2007-11-20)
CPLD_SPI\an485_design_example\modelsim\wave.bmp (406614, 2007-02-10)
CPLD_SPI\an485_design_example\modelsim\wave.do (1440, 2007-02-10)
CPLD_SPI\an485_design_example\modelsim\work (0, 2001-01-01)
CPLD_SPI\an485_design_example\modelsim\work\_info (649, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master (0, 2001-01-01)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master\verilog.psm (34033, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master\_primary.dat (2997, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_@master\_primary.vhd (583, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test (0, 2001-01-01)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test\verilog.psm (63144, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test\_primary.dat (7005, 2007-02-25)
CPLD_SPI\an485_design_example\modelsim\work\@s@p@i_master_test\_primary.vhd (90, 2007-02-25)
CPLD_SPI\an485_design_example\quartus (0, 2001-01-01)
CPLD_SPI\an485_design_example\quartus\SPI_Master.asm.rpt (7640, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.done (26, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.dpf (239, 2007-02-25)
CPLD_SPI\an485_design_example\quartus\SPI_Master.fit.rpt (72737, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.fit.smsg (334, 2007-11-22)
CPLD_SPI\an485_design_example\quartus\SPI_Master.fit.summary (371, 2007-11-22)
... ...
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