文件列表:

adc12d1600_ok\proj\adc12d1800\adc12d1800.gise (13000, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc12d1800.xise (38009, 2015-12-23)
adc12d1600_ok\proj\adc12d1800\adc_verif.bgn (9066, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.bit (20273550, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.bld (2134, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.cmd_log (1732, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.cpj (1318684, 2015-11-19)
adc12d1600_ok\proj\adc12d1800\adc_verif.drc (1087, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.lso (6, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.ncd (941570, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.ngc (150058, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.ngd (2044277, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.ngr (198311, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.pad (68086, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.par (19333, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.pcf (262002, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.prj (360, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.ptwx (18868, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.stx (0, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.syr (142273, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.twr (83805, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.twx (103278, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.unroutes (362, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.ut (742, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.xpi (46, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif.xst (1101, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_201512241435.cpj (200323, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_bitgen.xwbt (372, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_envsettings.html (17932, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_guide.ncd (941570, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_map.map (30265, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_map.mrp (75740, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_map.ncd (460747, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_map.ngm (4334703, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_map.xrpt (86773, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_ngdbuild.xrpt (20548, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_pad.csv (68119, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_pad.txt (348629, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_par.xrpt (722937, 2016-01-28)
adc12d1600_ok\proj\adc12d1800\adc_verif_summary.html (22234, 2016-01-28)
... ...

The following files were generated for 'vio' in directory E:\FPGA_Project\CLDSP_59\V7X485T_TEST_AD_DA_TOP\adc12d1600_ok\proj\adc12d1800\ipcore_dir\ XCO file generator: Generate an XCO file for compatibility with legacy flows. * vio.xco Creates an implementation netlist: Creates an implementation netlist for the IP. * vio.cdc * vio.constraints/vio.ucf * vio.constraints/vio.xdc * vio.ngc * vio.ucf * vio.v * vio.veo * vio.xdc * vio_xmdf.tcl IP Symbol Generator: Generate an IP symbol based on the current project options'. * vio.asy SYM file generator: Generate a SYM file for compatibility with legacy flows * vio.sym Generate ISE subproject: Create an ISE subproject for use when including this core in ISE designs * _xmsgs/pn_parser.xmsgs * vio.gise * vio.xise Deliver Readme: Readme file for the IP. * vio_readme.txt Generate FLIST file: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. * vio_flist.txt Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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