DDR3_SO_DIMM
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：15032KB
下载次数：50
上传日期：2017-04-10 15:46:26
上 传 者：
lcqwell
说明： 为FPGA，ddr3的IP核程序，实现ddr3芯片的读写操作。程序实现速度快，效率高。
(For FPGA, DDR3 IP core program, DDR3 chip read and write operations. Program implementation speed, high efficiency.)
文件列表:
DDR3_SO_DIMM (0, 2017-04-10)
DDR3_SO_DIMM\DDR3_SO_DIMM.gise (11501, 2017-04-10)
DDR3_SO_DIMM\DDR3_SO_DIMM.xise (39905, 2016-11-23)
DDR3_SO_DIMM\_ngo (0, 2016-12-02)
DDR3_SO_DIMM\_ngo\example_top_cs_signalbrowser.ngo (10524154, 2016-12-02)
DDR3_SO_DIMM\_ngo\example_top_cs_signalbrowser.ver (20, 2016-12-02)
DDR3_SO_DIMM\_xmsgs (0, 2016-12-02)
DDR3_SO_DIMM\_xmsgs\ngcbuild.xmsgs (367, 2016-12-02)
DDR3_SO_DIMM\_xmsgs\pn_parser.xmsgs (2139, 2017-04-10)
DDR3_SO_DIMM\_xmsgs\xst.xmsgs (1211214, 2016-12-02)
DDR3_SO_DIMM\ddr3_cmd_con.v (4948, 2016-04-05)
DDR3_SO_DIMM\ddr3_rd_con.v (4661, 2016-04-06)
DDR3_SO_DIMM\ddr3_test.cdc (87663, 2016-12-02)
DDR3_SO_DIMM\ddr3_test_to_user_switch.v (3360, 2016-04-05)
DDR3_SO_DIMM\ddr3_user_app.v (10920, 2016-04-07)
DDR3_SO_DIMM\ddr3_user_app_con.v (19942, 2016-04-09)
DDR3_SO_DIMM\ddr3_wr_con.v (8607, 2016-04-07)
DDR3_SO_DIMM\example_top.cmd_log (128, 2016-12-02)
DDR3_SO_DIMM\example_top.lso (6, 2016-12-02)
DDR3_SO_DIMM\example_top.ngc (9468711, 2016-12-02)
DDR3_SO_DIMM\example_top.ngr (11983484, 2016-12-02)
DDR3_SO_DIMM\example_top.prj (5209, 2016-12-02)
DDR3_SO_DIMM\example_top.stx (0, 2016-12-02)
DDR3_SO_DIMM\example_top.syr (1441865, 2016-12-02)
DDR3_SO_DIMM\example_top.xst (1105, 2016-12-02)
DDR3_SO_DIMM\example_top_bitgen.xwbt (293, 2013-01-05)
DDR3_SO_DIMM\example_top_cs.blc (1005, 2016-12-02)
DDR3_SO_DIMM\example_top_cs.ngc (10524154, 2016-12-02)
DDR3_SO_DIMM\example_top_envsettings.html (9312, 2017-04-10)
DDR3_SO_DIMM\example_top_guide.ncd (8279114, 2013-01-05)
DDR3_SO_DIMM\example_top_summary.html (5519, 2017-04-10)
DDR3_SO_DIMM\example_top_xst.xrpt (23269, 2016-12-02)
DDR3_SO_DIMM\initial_addr_gen.cmd_log (297, 2016-04-07)
DDR3_SO_DIMM\initial_addr_gen.v (14525, 2016-04-05)
DDR3_SO_DIMM\ipcore_dir (0, 2016-12-28)
DDR3_SO_DIMM\ipcore_dir\DDR3_SO_DIMM (0, 2016-11-11)
DDR3_SO_DIMM\ipcore_dir\DDR3_SO_DIMM\DDR3_SO_DIMM.csv (5809, 2016-04-05)
DDR3_SO_DIMM\ipcore_dir\DDR3_SO_DIMM\datasheet.txt (2449, 2016-04-05)
DDR3_SO_DIMM\ipcore_dir\DDR3_SO_DIMM\docs (0, 2016-11-11)
... ...
The design files are located at
C:/Users/k/Desktop/IQ_SFP/DDR3_4G_SO_DIMM/DDR3_SO_DIMM/ipcore_dir:
- DDR3_SO_DIMM.veo:
veo template file containing code that can be used as a model
for instantiating a CORE Generator module in a HDL design.
- DDR3_SO_DIMM.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
- DDR3_SO_DIMM_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
- DDR3_SO_DIMM_readme.txt:
Text file indicating the files generated and how they are used.
- DDR3_SO_DIMM_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
- DDR3_SO_DIMM.csv:
Includes the pin out information which is used as support file
for PlanAhead.
- DDR3_SO_DIMM.gise and DDR3_SO_DIMM.xise:
ISE Project Navigator support files. These are generated files and
should not be edited directly.
- DDR3_SO_DIMM directory.
In the DDR3_SO_DIMM directory, three folders are created:
- docs:
This folder contains MIG user guide.
- example_design:
This folder includes script files to implement and simulate the design.
This includes the traffic generator RTL modules and example_top module.
- user_design:
This folder includes the all RTL modules of controller, phy and
user interface RTL modules. UCF file is provided.
The example_design and user_design folders contain several other folders
and files. All these output folders are discussed in more detail in
MIG user guide (ug586_7Series_MIS.pdf) located in docs folder.
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