pll
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：2046KB
下载次数：3
上传日期：2017-04-12 15:55:56
上 传 者：
5093676
说明： 基于ISE软件调用 Xilinx 提供的 PLL 核来产生不同频率的时钟, 并把其中的一个时钟输出到 FPGA 外部 IO 上。
(Generating clocks of different frequencies based software calls provided by Xilinx ISE PLL core, and wherein the output of a clock external to the FPGA IO.)
文件列表:
pll\_ngo (0, 2017-04-07)
pll\_ngo\cs_icon_pro (0, 2017-04-07)
pll\_ngo\cs_icon_pro\_xmsgs (0, 2017-04-07)
pll\_ngo\cs_icon_pro\_xmsgs\xst.xmsgs (26922, 2017-04-07)
pll\_ngo\cs_icon_pro\coregen.cgc (16250, 2017-04-07)
pll\_ngo\cs_icon_pro\coregen.cgp (520, 2017-04-07)
pll\_ngo\cs_icon_pro\coregen.log (2412, 2017-04-07)
pll\_ngo\cs_icon_pro\generate_icon_pro.xco (684, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro.gise (1167, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro.ucf (375, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro.vhd (947, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro.vho (1366, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro.xco (1660, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro.xise (41251, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro_flist.txt (199, 2017-04-07)
pll\_ngo\cs_icon_pro\icon_pro_xmdf.tcl (2504, 2017-04-07)
pll\_ngo\cs_icon_pro\tmp (0, 2017-04-07)
pll\_ngo\cs_icon_pro\tmp\_cg (0, 2017-04-07)
pll\_ngo\cs_icon_pro\tmp\_xmsgs (0, 2017-04-07)
pll\_ngo\cs_icon_pro\tmp\_xmsgs\pn_parser.xmsgs (790, 2017-04-07)
pll\_ngo\cs_ila_pro_0 (0, 2017-04-07)
pll\_ngo\cs_ila_pro_0\_xmsgs (0, 2017-04-07)
pll\_ngo\cs_ila_pro_0\_xmsgs\xst.xmsgs (30076, 2017-04-07)
pll\_ngo\cs_ila_pro_0\coregen.cgc (43929, 2017-04-07)
pll\_ngo\cs_ila_pro_0\coregen.cgp (520, 2017-04-07)
pll\_ngo\cs_ila_pro_0\coregen.log (2440, 2017-04-07)
pll\_ngo\cs_ila_pro_0\generate_ila_pro_0.xco (3194, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.cdc (1160, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.gise (1169, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.ucf (463, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.vhd (1062, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.vho (1537, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.xco (4231, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0.xise (41266, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0_flist.txt (225, 2017-04-07)
pll\_ngo\cs_ila_pro_0\ila_pro_0_xmdf.tcl (2683, 2017-04-07)
pll\_ngo\cs_ila_pro_0\tmp (0, 2017-04-07)
pll\_ngo\cs_ila_pro_0\tmp\_cg (0, 2017-04-07)
... ...
The following files were generated for 'icon_pro' in directory
C:\Users\Administrator\Desktop\dy\exc\pll\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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