bch_dec_enc_dcd
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：1071KB
下载次数：49
上传日期：2017-04-24 11:26:10
上 传 者：
morning小小
说明： 关于BCH的编码器和译码器，可实现16位，32位，64位，128位的编码和译码纠错，2位纠错，Verilog实现
(On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation)
文件列表:
bch_dec_enc_dcd (0, 2017-04-19)
bch_dec_enc_dcd\doc (0, 2017-04-19)
bch_dec_enc_dcd\doc\bch_dec_dcd.pdf (538585, 2011-04-26)
bch_dec_enc_dcd\rtl (0, 2017-04-19)
bch_dec_enc_dcd\rtl\univ (0, 2017-04-20)
bch_dec_enc_dcd\rtl\univ\bch_dec_dcd_univ_top.v (2251, 2011-04-26)
bch_dec_enc_dcd\rtl\univ\bch_dec_enc_univ_top.v (1220, 2011-04-25)
bch_dec_enc_dcd\rtl\univ\bch_dec_fn.v (1940, 2011-04-25)
bch_dec_enc_dcd\rtl\univ\enc_synd_calc_univ.v (2802, 2011-04-26)
bch_dec_enc_dcd\rtl\univ\enc_synd_gen_fn_127.v (7774, 2011-04-24)
bch_dec_enc_dcd\rtl\univ\enc_synd_gen_fn_255.v (18333, 2011-04-24)
bch_dec_enc_dcd\rtl\univ\enc_synd_gen_fn_31.v (1283, 2011-04-26)
bch_dec_enc_dcd\rtl\univ\enc_synd_gen_fn_63.v (3137, 2011-04-25)
bch_dec_enc_dcd\rtl\univ\err_patt_dcd_fn_127.v (1659029, 2011-04-24)
bch_dec_enc_dcd\rtl\univ\err_patt_dcd_fn_255.v (11881885, 2011-04-24)
bch_dec_enc_dcd\rtl\univ\err_patt_dcd_fn_31.v (81214, 2011-04-25)
bch_dec_enc_dcd\rtl\univ\err_patt_dcd_fn_63.v (508511, 2011-04-25)
bch_dec_enc_dcd\rtl\univ\err_pat_dcd_rom_univ.v (2163, 2011-04-26)
bch_dec_enc_dcd\rtl\univ\tags (2229, 2017-04-19)
bch_dec_enc_dcd\rtl\univ\timescale.v (216, 2011-04-25)
bch_dec_enc_dcd\sim (0, 2017-04-19)
bch_dec_enc_dcd\sim\univ (0, 2017-04-19)
bch_dec_enc_dcd\sim\univ\dcd_univ_tb_top_n.v (7335, 2011-04-26)
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