OpenCoreUSB2IP
所属分类：USB编程
开发工具：VHDL
文件大小：192KB
下载次数：8
上传日期：2017-05-02 10:58:40
上 传 者：
xlt
说明： OpenCore 的 USB2.0 IP
(OpenCore 的 USB2.0 IP全套资料，包括源代码、设计文档等)
文件列表:
USB2.0 IP\bench\CVS\Entries (14, 2001-08-19)
USB2.0 IP\bench\CVS\Repository (16, 2001-08-19)
USB2.0 IP\bench\CVS\Root (13, 2001-08-19)
USB2.0 IP\bench\verilog\CVS\Entries (2, 2001-08-19)
USB2.0 IP\bench\verilog\CVS\Repository (24, 2001-08-19)
USB2.0 IP\bench\verilog\CVS\Root (13, 2001-08-19)
USB2.0 IP\doc\CVS\Entries (135, 2001-08-19)
USB2.0 IP\doc\CVS\Repository (14, 2001-08-19)
USB2.0 IP\doc\CVS\Root (13, 2001-08-19)
USB2.0 IP\doc\STATUS.txt (1573, 2001-08-03)
USB2.0 IP\doc\usb_doc.pdf (321938, 2001-08-10)
USB2.0 IP\rtl\CVS\Entries (14, 2001-08-19)
USB2.0 IP\rtl\CVS\Repository (14, 2001-08-19)
USB2.0 IP\rtl\CVS\Root (13, 2001-08-19)
USB2.0 IP\rtl\verilog\CVS\Entries (714, 2001-08-19)
USB2.0 IP\rtl\verilog\CVS\Repository (22, 2001-08-19)
USB2.0 IP\rtl\verilog\CVS\Root (13, 2001-08-19)
USB2.0 IP\rtl\verilog\usbf_crc16.v (4796, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_crc5.v (4159, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_defines.v (9328, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_ep_rf.v (12004, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_ep_rf_dummy.v (5399, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_idma.v (12769, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_mem_arb.v (5600, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_pa.v (8620, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_pd.v (12023, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_pe.v (27292, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_pl.v (13271, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_rf.v (49805, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_top.v (16897, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_utmi_if.v (6551, 2001-08-03)
USB2.0 IP\rtl\verilog\usbf_utmi_ls.v (16592, 2001-08-10)
USB2.0 IP\rtl\verilog\usbf_wb.v (7189, 2001-08-10)
USB2.0 IP\sim\CVS\Entries (14, 2001-08-19)
USB2.0 IP\sim\CVS\Repository (14, 2001-08-19)
USB2.0 IP\sim\CVS\Root (13, 2001-08-19)
USB2.0 IP\sim\rtl_sim\bin\CVS\Entries (2, 2001-08-19)
USB2.0 IP\sim\rtl_sim\bin\CVS\Repository (26, 2001-08-19)
USB2.0 IP\sim\rtl_sim\bin\CVS\Root (13, 2001-08-19)
... ...
The USB 2.0 Function Project Page is:
http://www.opencores.org/cores/usb/
To find out more about me (Rudolf Usselmann), please visit:
http://www.asics.ws
Directory Structure
-------------------
[core_root]
|
+-doc Documentation
|
+-bench--+ Test Bench
| +- verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-rtl----+ Core RTL Sources
| +-verilog Verilog Sources
| +-vhdl VHDL Sources
|
+-sim----+
| +-rtl_sim---+ Functional verification Directory
| | +-bin Makefiles/Run Scripts
| | +-run Working Directory
| |
| +-gate_sim--+ Functional & Timing Gate Level
| | Verification Directory
| +-bin Makefiles/Run Scripts
| +-run Working Directory
|
+-lint--+ Lint Directory Tree
| +-bin Makefiles/Run Scripts
| +-run Working Directory
| +-log Linter log & result files
|
+-syn---+ Synthesis Directory Tree
| +-bin Synthesis Scripts
| +-run Working Directory
| +-log Synthesis log files
| +-out Synthesis Output
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